-
- // last bit = 0 then fdt = 1172, in case of 0x26 (7-bit command, LSB first!)
- // last bit = 1 then fdt = 1236, in case of 0x52 (7-bit command, LSB first!)
- if(fdt_counter == 11'd740) fdt_indicator = 1'b1;
+ // ------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ // relevant for TAGSIM_MOD only. Timing of Tag's answer to a command received from a reader
+ // ISO14443-3 specifies:
+ // fdt = 1172, if last bit was 0.
+ // fdt = 1236, if last bit was 1.
+ // the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
+ // The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
+ if(fdt_counter == 11'd740) fdt_indicator = 1'b1; // fdt_indicator is true for 740 <= fdt_counter <= 1148. Ready to buffer data. (?)
+ // Shouldn' this be 1236 - 720 = 516? (The mod_sig_buf can buffer 46 data bits,
+ // i.e. a maximum delay of 46 * 16 = 720 adc_clk ticks)