fix 'hf iclass sim':

[proxmark3-svn] / fpga / hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index 92ebcb51387c48be14eef162931115c68096b04b..097b8a084a3e5daadca9d6e31d4f8ea64ee8527f 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -33,15 +33,33 @@ module hi_simulate(
     output dbg;
     input [2:0] mod_type;
 
     output dbg;
     input [2:0] mod_type;
 

+assign adc_clk = ck_1356meg;

 
 // The comparator with hysteresis on the output from the peak detector.
 reg after_hysteresis;
 
 // The comparator with hysteresis on the output from the peak detector.
 reg after_hysteresis;

-assign adc_clk = ck_1356meg;
+reg [11:0] has_been_low_for;

 
 always @(negedge adc_clk)
 begin
 
 always @(negedge adc_clk)
 begin

-    if(& adc_d[7:5]) after_hysteresis = 1'b1;           // if (adc_d >= 224)
-    else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;   // if (adc_d <= 31)
+    if (& adc_d[7:5]) after_hysteresis <= 1'b1;           // if (adc_d >= 224)
+    else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0;   // if (adc_d <= 31)
+
+       if (adc_d >= 224)
+    begin
+        has_been_low_for <= 12'd0;
+    end
+    else
+    begin
+        if (has_been_low_for == 12'd4095)
+        begin
+            has_been_low_for <= 12'd0;
+            after_hysteresis <= 1'b1;
+        end
+        else
+               begin
+            has_been_low_for <= has_been_low_for + 1;
+               end     
+    end

 end
 
 
 end