Initial commit for the firmware. Used the 20090306_ela version as baseline.

[proxmark3-svn] / fpga / fpga.ucf

diff --git a/fpga/fpga.ucf b/fpga/fpga.ucf
new file mode 100644 (file)
index 0000000..bf0d40b
--- /dev/null
+++ b/fpga/fpga.ucf
@@ -0,0 +1,41 @@
+# See the schematic for the pin assignment.\r
+\r
+NET "adc_d<0>"  LOC = "P62"  ; \r
+NET "adc_d<1>"  LOC = "P60"  ; \r
+NET "adc_d<2>"  LOC = "P58"  ; \r
+NET "adc_d<3>"  LOC = "P57"  ; \r
+NET "adc_d<4>"  LOC = "P56"  ; \r
+NET "adc_d<5>"  LOC = "P55"  ; \r
+NET "adc_d<6>"  LOC = "P54"  ; \r
+NET "adc_d<7>"  LOC = "P53"  ; \r
+#NET "cross_hi"  LOC = "P88"  ; \r
+#NET "miso"  LOC = "P40"  ; \r
+#PACE: Start of Constraints generated by PACE\r
+\r
+#PACE: Start of PACE I/O Pin Assignments\r
+NET "adc_clk"  LOC = "P46"  ; \r
+NET "adc_noe"  LOC = "P47"  ; \r
+NET "ck_1356meg"  LOC = "P91"  ; \r
+NET "ck_1356megb"  LOC = "P93"  ; \r
+NET "cross_lo"  LOC = "P87"  ; \r
+NET "dbg"  LOC = "P22"  ; \r
+NET "mosi"  LOC = "P43"  ; \r
+NET "ncs"  LOC = "P44"  ; \r
+NET "pck0"  LOC = "P36"  ; \r
+NET "pwr_hi"  LOC = "P80"  ; \r
+NET "pwr_lo"  LOC = "P81"  ; \r
+NET "pwr_oe1"  LOC = "P82"  ; \r
+NET "pwr_oe2"  LOC = "P83"  ; \r
+NET "pwr_oe3"  LOC = "P84"  ; \r
+NET "pwr_oe4"  LOC = "P86"  ; \r
+NET "spck"  LOC = "P39"  ; \r
+NET "ssp_clk"  LOC = "P71"  ; \r
+NET "ssp_din"  LOC = "P32"  ; \r
+NET "ssp_dout"  LOC = "P34"  ; \r
+NET "ssp_frame"  LOC = "P31"  ; \r
+\r
+#PACE: Start of PACE Area Constraints\r
+\r
+#PACE: Start of PACE Prohibit Constraints\r
+\r
+#PACE: End of Constraints generated by PACE\r