// mode once it is configured.
//-----------------------------------------------------------------------------
+#include "fpgaloader.h"
+
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
-#include "fpgaloader.h"
+#include "apps.h"
+#include "fpga.h"
#include "proxmark3.h"
#include "util.h"
#include "string.h"
#include "BigBuf.h"
#include "zlib.h"
-extern void Dbprintf(const char *fmt, ...);
-
// remember which version of the bitstream we have already downloaded to the FPGA
-static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
+static int downloaded_bitstream = 0;
// this is where the bitstreams are located in memory:
extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
static uint8_t *fpga_image_ptr = NULL;
static uint32_t uncompressed_bytes_cnt;
-static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
-#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
#define OUTPUT_BUFFER_LEN 80
-#define FPGA_INTERLEAVE_SIZE 288
//-----------------------------------------------------------------------------
// Set up the Serial Peripheral Interface as master
}
//-----------------------------------------------------------------------------
-// Set up the synchronous serial port, with the one set of options that we
-// always use when we are talking to the FPGA. Both RX and TX are enabled.
+// Set up the synchronous serial port with the set of options that fits
+// the FPGA mode. Both RX and TX are always enabled.
//-----------------------------------------------------------------------------
-void FpgaSetupSsc(void)
+void FpgaSetupSsc(uint8_t FPGA_mode)
{
// First configure the GPIOs, and get ourselves a clock.
AT91C_BASE_PIOA->PIO_ASR =
// on RX clock rising edge, sampled on falling edge
AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
- // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
+ // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync
// pulse, no output sync
- AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+ if ((FPGA_mode & 0xe0) == FPGA_MAJOR_MODE_HF_READER_RX_XCORR) {
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+ } else {
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+ }
- // clock comes from TK pin, no clock output, outputs change on falling
+ // TX clock comes from TK pin, no clock output, outputs change on falling
// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
// ourselves, not to another buffer). The stuff to manipulate those buffers
// is in apps.h, because it should be inlined, for speed.
//-----------------------------------------------------------------------------
-bool FpgaSetupSscDma(uint8_t *buf, int len)
+bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count)
{
- if (buf == NULL) {
- return false;
- }
-
- AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
- AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
- AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
- AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
- AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
- AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
-
- return true;
+ if (buf == NULL) return false;
+
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
+ AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
+ AT91C_BASE_PDC_SSC->PDC_RCR = sample_count; // transfer this many samples
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
+ AT91C_BASE_PDC_SSC->PDC_RNCR = sample_count; // ... with same number of samples AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
+ return true;
}
+//----------------------------------------------------------------------------
+// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
+// each call.
+//----------------------------------------------------------------------------
static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
fpga_image_ptr = output_buffer;
int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
- if (res != Z_OK) {
+ if (res != Z_OK)
Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
- }
- if (res < 0) {
+
+ if (res < 0)
return res;
- }
}
uncompressed_bytes_cnt++;
return *fpga_image_ptr++;
}
-
+//----------------------------------------------------------------------------
+// Undo the interleaving of several FPGA config files. FPGA config files
+// are combined into one big file:
+// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
+//----------------------------------------------------------------------------
static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
- while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
+ while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % fpga_bitstream_num != (bitstream_version - 1)) {
// skip undesired data belonging to other bitstream_versions
get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
}
static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
{
- Dbprintf("zlib requested %d bytes", items*size);
return BigBuf_malloc(items*size);
}
static void fpga_inflate_free(voidpf opaque, voidpf address)
{
- Dbprintf("zlib frees memory");
- BigBuf_free_keep_EM();
+ BigBuf_free(); BigBuf_Clear_ext(false);
}
+//----------------------------------------------------------------------------
+// Initialize decompression of the respective (HF or LF) FPGA stream
+//----------------------------------------------------------------------------
static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
// initialize z_stream structure for inflate:
compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
- compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
+ compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;
compressed_fpga_stream->next_out = output_buffer;
compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
compressed_fpga_stream->zfree = &fpga_inflate_free;
- inflateInit2(compressed_fpga_stream, 15);
+ inflateInit2(compressed_fpga_stream, 0);
fpga_image_ptr = output_buffer;
header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
}
- // Check for a valid .bit file (starts with _bitparse_fixed_header)
- if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
+ // Check for a valid .bit file (starts with bitparse_fixed_header)
+ if(memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
return true;
} else {
return false;
static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
- Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
+ //Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
int i=0;
DownloadFPGA_byte(b);
}
- Dbprintf("%d bytes loaded into FPGA", i);
-
// continue to clock FPGA until ready signal goes high
i=100000;
while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
}
-//-----------------------------------------------------------------------------
-// Find out which FPGA image format is stored in flash, then call DownloadFPGA
-// with the right parameters to download the image
-//-----------------------------------------------------------------------------
+//----------------------------------------------------------------------------
+// Check which FPGA image is currently loaded (if any). If necessary
+// decompress and load the correct (HF or LF) image to the FPGA
+//----------------------------------------------------------------------------
void FpgaDownloadAndGo(int bitstream_version)
{
z_stream compressed_fpga_stream;
- uint8_t output_buffer[OUTPUT_BUFFER_LEN];
+ uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
// check whether or not the bitstream is already loaded
if (downloaded_bitstream == bitstream_version)
return;
+ // make sure that we have enough memory to decompress
+ BigBuf_free(); BigBuf_Clear_ext(false);
+
if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
return;
}
unsigned int bitstream_length;
- if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
+ if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
downloaded_bitstream = bitstream_version;
}
inflateEnd(&compressed_fpga_stream);
-
-}
-
-
-void FpgaGatherVersion(int bitstream_version, char *dst, int len)
-{
- unsigned int fpga_info_len;
- char tempstr[40];
- z_stream compressed_fpga_stream;
- uint8_t output_buffer[OUTPUT_BUFFER_LEN];
- dst[0] = '\0';
-
- if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
- return;
- }
-
- if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
- for (uint16_t i = 0; i < fpga_info_len; i++) {
- char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
- if (i < sizeof(tempstr)) {
- tempstr[i] = c;
- }
- }
- if (!memcmp("fpga_lf", tempstr, 7))
- strncat(dst, "LF ", len-1);
- else if (!memcmp("fpga_hf", tempstr, 7))
- strncat(dst, "HF ", len-1);
- }
- strncat(dst, "FPGA image built", len-1);
- if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
- strncat(dst, " for ", len-1);
- for (uint16_t i = 0; i < fpga_info_len; i++) {
- char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
- if (i < sizeof(tempstr)) {
- tempstr[i] = c;
- }
- }
- strncat(dst, tempstr, len-1);
- }
- if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
- strncat(dst, " on ", len-1);
- for (uint16_t i = 0; i < fpga_info_len; i++) {
- char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
- if (i < sizeof(tempstr)) {
- tempstr[i] = c;
- }
- }
- strncat(dst, tempstr, len-1);
- }
- if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
- strncat(dst, " at ", len-1);
- for (uint16_t i = 0; i < fpga_info_len; i++) {
- char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
- if (i < sizeof(tempstr)) {
- tempstr[i] = c;
- }
- }
- strncat(dst, tempstr, len-1);
- }
+ // turn off antenna
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- inflateEnd(&compressed_fpga_stream);
-
-}
+ // free eventually allocated BigBuf memory
+ BigBuf_free(); BigBuf_Clear_ext(false);
+}
//-----------------------------------------------------------------------------
HIGH(whichGpio);
}
+
+void Fpga_print_status(void) {
+ Dbprintf("Currently loaded FPGA image:");
+ Dbprintf(" %s", fpga_version_information[downloaded_bitstream-1]);
+}
+
+int FpgaGetCurrent() {
+ return downloaded_bitstream;
+}
projects / proxmark3-svn / blobdiff