FPGA changes (#803)
authorpwpiwi <pwpiwi@users.noreply.github.com>
Sun, 24 Mar 2019 17:11:41 +0000 (18:11 +0100)
committerGitHub <noreply@github.com>
Sun, 24 Mar 2019 17:11:41 +0000 (18:11 +0100)
commit5ea2a24839c71ba6e58af937a392a6204b8b4696
tree93400aa632102d874504de570c3053ef0e183043
parentca8a3478d949a03953129ec34d209a9c80079252
FPGA changes (#803)

* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame
* get rid of most of the warnings when compiling the HF verilog sources
* refactoring the constants in Verilog sources
18 files changed:
armsrc/appmain.c
armsrc/fpgaloader.c
armsrc/fpgaloader.h
armsrc/iso14443b.c
armsrc/iso14443b.h
armsrc/iso15693.c
armsrc/legicrf.c
fpga/Makefile
fpga/fpga.ucf
fpga/fpga_hf.bit
fpga/fpga_hf.v
fpga/hi_get_trace.v
fpga/hi_iso14443a.v
fpga/hi_read_rx_xcorr.v [deleted file]
fpga/hi_read_tx.v [deleted file]
fpga/hi_reader.v [new file with mode: 0644]
fpga/hi_simulate.v
fpga/hi_sniffer.v
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