FIX: Even the US clock had the issues with not resetting properly. Now its always...

diff --git a/armsrc/util.c b/armsrc/util.c
index b4d3dec5994eebaf50670291ce88a41e83d73fc9..37fe3f4396a79be827fd5216c28b1b5973f0c6ae 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -56,7 +56,7 @@ uint32_t reflect(uint32_t v, int b) {
                        v |=  BITMASK((b-1)-i);
                else
                        v &= ~BITMASK((b-1)-i);
                        v |=  BITMASK((b-1)-i);
                else
                        v &= ~BITMASK((b-1)-i);

-               t>>=1;
+               t >>= 1;

        }
        return v;
 }
        }
        return v;
 }


@@ -340,16 +340,25 @@ void StartCountUS() {
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
        
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
        

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;

        AT91C_BASE_TCB->TCB_BCR = 1;
        AT91C_BASE_TCB->TCB_BCR = 1;

-       }
+       
+       while (AT91C_BASE_TC1->TC_CV >= 1);
+}

 
 uint32_t RAMFUNC GetCountUS(){
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
        //  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
        return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
 
 uint32_t RAMFUNC GetCountUS(){
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
        //  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
        return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 

+       //return (AT91C_BASE_TC1->TC_CV << 16) | ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
+}
+void ResetUSClock(void) {      
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC1->TC_CV >= 1);

 }
 
 // static uint32_t GlobalUsCounter = 0;
 }
 
 // static uint32_t GlobalUsCounter = 0;


@@ -424,9 +433,9 @@ void StartCountSspClk() {
 }
 void ResetSspClk(void) {       
        //enable clock of timer and software trigger
 }
 void ResetSspClk(void) {       
        //enable clock of timer and software trigger

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_SWTRG;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;

 }
 
 uint32_t RAMFUNC GetCountSspClk(){
 }
 
 uint32_t RAMFUNC GetCountSspClk(){

diff --git a/armsrc/util.h b/armsrc/util.h
index 05364519e6c09565cf1e64f0b36dda4f4f92edd9..7a539226dd7d2d8d01a1bec6b507c22099e50de7 100644 (file)
--- a/armsrc/util.h
+++ b/armsrc/util.h
@@ -64,6 +64,7 @@ uint32_t RAMFUNC GetTickCount();
 
 void StartCountUS();
 uint32_t RAMFUNC GetCountUS();
 
 void StartCountUS();
 uint32_t RAMFUNC GetCountUS();

+void ResetUSClock(void);

 //uint32_t RAMFUNC GetDeltaCountUS();
 
 void StartCountSspClk();
 //uint32_t RAMFUNC GetDeltaCountUS();
 
 void StartCountSspClk();