Merge pull request #8 from pwpiwi/master
authorholiman <martin@swende.se>
Tue, 25 Mar 2014 20:49:05 +0000 (21:49 +0100)
committerholiman <martin@swende.se>
Tue, 25 Mar 2014 20:49:05 +0000 (21:49 +0100)
add .gitignore and merge svn r852

.gitignore [new file with mode: 0644]
armsrc/fpgaloader.c
armsrc/iso14443a.c
armsrc/mifaresniff.c
armsrc/util.c
client/cmdhfmf.c
fpga/fpga.bit
fpga/hi_iso14443a.v

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..a43a00f
--- /dev/null
@@ -0,0 +1,27 @@
+# .gitignore
+# don't push these files to the repository
+
+*.o
+*.a
+*.d
+*.elf
+*.s19
+*.map
+*.bin
+*.dll
+*.moc.cpp
+*.exe
+proxmark
+flasher
+version.c
+
+fpga/*
+!fpga/fpga.bit
+!fpga/*.v
+!fpga/Makefile
+!fpga/fpga.ucf
+!fpga/xst.scr
+!fpga/go.bat
+!fpga/sim.tcl
+
+
index 1e728e11884be4bbb438756266293be95325c757..d63310a3525914ee82be4ad7a14b8573c435cbee 100644 (file)
@@ -115,11 +115,11 @@ void FpgaSetupSsc(void)
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
-       // pulse, no output sync, start on positive-going edge of sync
+       // pulse, no output sync
        AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
 
        // clock comes from TK pin, no clock output, outputs change on falling
-       // edge of TK, sample on rising edge of TK
+       // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
        AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
 
        // tx framing is the same as the rx framing
index b105e792d3af7f5d4ca7e672a378912764af7b1e..9afe0788c666a79ac4ef2f4f9da09a6b70cabed4 100644 (file)
@@ -42,15 +42,14 @@ static uint8_t iso14_pcb_blocknum = 0;
 //
 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
 //
-// When the PM acts as reader and is receiving, it takes 
-// 3 ticks for the A/D conversion
-// 10 ticks ( 16 on average) delay in the modulation detector.
-// 6 ticks until the SSC samples the first data
-// 7*16 ticks to complete the transfer from FPGA to ARM
-// 8 ticks to the next ssp_clk rising edge
+// When the PM acts as reader and is receiving tag data, it takes
+// 3 ticks delay in the AD converter
+// 16 ticks until the modulation detector completes and sets curbit
+// 8 ticks until bit_to_arm is assigned from curbit
+// 8*16 ticks for the transfer from FPGA to ARM
 // 4*16 ticks until we measure the time
 // - 8*16 ticks because we measure the time of the previous transfer 
-#define DELAY_AIR2ARM_AS_READER (3 + 10 + 6 + 7*16 + 8 + 4*16 - 8*16) 
+#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16) 
 
 // When the PM acts as a reader and is sending, it takes
 // 4*16 ticks until we can write data to the sending hold register
@@ -61,15 +60,15 @@ static uint8_t iso14_pcb_blocknum = 0;
 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
 
 // When the PM acts as tag and is receiving it takes
-// 12 ticks delay in the RF part,
+// 2 ticks delay in the RF part (for the first falling edge),
 // 3 ticks for the A/D conversion,
 // 8 ticks on average until the start of the SSC transfer,
 // 8 ticks until the SSC samples the first data
 // 7*16 ticks to complete the transfer from FPGA to ARM
 // 8 ticks until the next ssp_clk rising edge
-// 3*16 ticks until we measure the time 
+// 4*16 ticks until we measure the time 
 // - 8*16 ticks because we measure the time of the previous transfer 
-#define DELAY_AIR2ARM_AS_TAG (12 + 3 + 8 + 8 + 7*16 + 8 + 3*16 - 8*16)
+#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
  
 // The FPGA will report its internal sending delay in
 uint16_t FpgaSendQueueDelay;
@@ -78,29 +77,30 @@ uint16_t FpgaSendQueueDelay;
 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
 
 // When the PM acts as tag and is sending, it takes
-// 5*16 ticks until we can write data to the sending hold register
+// 4*16 ticks until we can write data to the sending hold register
 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
 // 8 ticks until the first transfer starts
 // 8 ticks later the FPGA samples the data
 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
 // + 1 tick to assign mod_sig_coil
-#define DELAY_ARM2AIR_AS_TAG (5*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
+#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
 
 // When the PM acts as sniffer and is receiving tag data, it takes
 // 3 ticks A/D conversion
-// 16 ticks delay in the modulation detector (on average).
-// + 16 ticks until it's result is sampled.
+// 14 ticks to complete the modulation detection
+// 8 ticks (on average) until the result is stored in to_arm
 // + the delays in transferring data - which is the same for
 // sniffing reader and tag data and therefore not relevant
-#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 16 + 16
+#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8
  
-// When the PM acts as sniffer and is receiving tag data, it takes
-// 12 ticks delay in analogue RF receiver
+// When the PM acts as sniffer and is receiving reader data, it takes
+// 2 ticks delay in analogue RF receiver (for the falling edge of the 
+// start bit, which marks the start of the communication)
 // 3 ticks A/D conversion
-// 8 ticks on average until we sample the data.
+// 8 ticks on average until the data is stored in to_arm.
 // + the delays in transferring data - which is the same for
 // sniffing reader and tag data and therefore not relevant
-#define DELAY_READER_AIR2ARM_AS_SNIFFER (12 + 3 + 8) 
+#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8) 
 
 //variables used for timing purposes:
 //these are in ssp_clk cycles:
@@ -258,23 +258,7 @@ void UartReset()
        Uart.endTime = 0;
 }
 
-/* inline RAMFUNC Modulation_t MillerModulation(uint8_t b)
-{
-       // switch (b & 0x88) {
-               // case 0x00:   return MILLER_MOD_BOTH_HALVES;
-               // case 0x08:   return MILLER_MOD_FIRST_HALF;
-               // case 0x80:   return MILLER_MOD_SECOND_HALF;
-               // case 0x88:   return MILLER_MOD_NOMOD;
-       // }
-       // test the second cycle for a pause. For whatever reason the startbit tends to appear earlier than the rest.
-       switch (b & 0x44) {
-               case 0x00:      return MOD_BOTH_HALVES;
-               case 0x04:      return MOD_FIRST_HALF;
-               case 0x40:      return MOD_SECOND_HALF;
-               default:        return MOD_NOMOD;
-       }
-}
- */
+
 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
 {
@@ -398,10 +382,10 @@ static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
 static tDemod Demod;
 
 // Lookup-Table to decide if 4 raw bits are a modulation.
-// We accept three or four consecutive "1" in any position
+// We accept three or four "1" in any position
 const bool Mod_Manchester_LUT[] = {
        FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
-       FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,  TRUE
+       FALSE, FALSE, FALSE, TRUE,  FALSE, TRUE,  TRUE,  TRUE
 };
 
 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
@@ -646,7 +630,7 @@ void RAMFUNC SnoopIso14443a(uint8_t param) {
                previous_data = *data;
                rsamples++;
                data++;
-               if(data > dmaBuf + DMA_BUFFER_SIZE) {
+               if(data == dmaBuf + DMA_BUFFER_SIZE) {
                        data = dmaBuf;
                }
        } // main cycle
@@ -1423,7 +1407,7 @@ static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, bool correctionNeeded)
                i = 1;
        }
 
-       // clear receiving shift register and holding register
+       // clear receiving shift register and holding register
        while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
        b = AT91C_BASE_SSC->SSC_RHR; (void) b;
        while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
@@ -2593,11 +2577,12 @@ void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *
                //May just aswell send the collected ar_nr in the response aswell
                cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
        }
+
        if(flags & FLAG_NR_AR_ATTACK)
        {
                if(ar_nr_collected > 1) {
                        Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
-                       Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x",
+                       Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
                                         ar_nr_responses[0], // UID
                                        ar_nr_responses[1], //NT
                                        ar_nr_responses[2], //AR1
@@ -2608,7 +2593,7 @@ void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *
                } else {
                        Dbprintf("Failed to obtain two AR/NR pairs!");
                        if(ar_nr_collected >0) {
-                               Dbprintf("Only got these: UID=%08d, nonce=%08d, AR1=%08d, NR1=%08d",
+                               Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
                                                ar_nr_responses[0], // UID
                                                ar_nr_responses[1], //NT
                                                ar_nr_responses[2], //AR1
@@ -2762,7 +2747,7 @@ void RAMFUNC SniffMifare(uint8_t param) {
                previous_data = *data;
                sniffCounter++;
                data++;
-               if(data > dmaBuf + DMA_BUFFER_SIZE) {
+               if(data == dmaBuf + DMA_BUFFER_SIZE) {
                        data = dmaBuf;
                }
 
index bd9840e8cb4a8467e9b3c6b3719f0aede40a9d18..3e5570f9ce6e575ecd1b19f2f696b30d42b94b94 100644 (file)
@@ -93,7 +93,8 @@ bool RAMFUNC MfSniffLogic(const uint8_t *data, uint16_t len, uint32_t parity, ui
                }\r
                case SNF_ANTICOL2:{\r
                        if ((!reader) && (len == 5) && ((data[0] ^ data[1] ^ data[2] ^ data[3]) == data[4])) { // CL2 UID \r
-                               memcpy(sniffUID, data, 4);\r
+                               memcpy(sniffUID, sniffUID+4, 3);\r
+                               memcpy(sniffUID+3, data, 4);\r
                                sniffUIDType = SNF_UID_7;\r
                                sniffState = SNF_UID2;\r
                        }\r
index 6d34ae5e80f0f3cad520bdf480f75e9396956638..905bad253bf2d334ada7c37dd011eb079945ba1a 100644 (file)
@@ -363,8 +363,6 @@ void StartCountSspClk()
        //
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
-       // after the falling edge of ssp_frame, there is delay of 1/13,56MHz (73ns) until the next rising edge of ssp_clk. This are only a few
-       // processor cycles. We therefore may or may not be able to sync on this edge. Therefore better make sure that we miss it:
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
        // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
index adf456f8ee21eec6646c57c442677982940c678b..a26652566e812d353a6a1f739ed4a296902561f6 100644 (file)
@@ -1883,8 +1883,9 @@ int CmdHF14AMfSniff(const char *Cmd){
        printf("Press the key on pc keyboard to abort the client.\n");\r
        printf("-------------------------------------------------------------------------\n");\r
 \r
-  UsbCommand c = {CMD_MIFARE_SNIFFER, {0, 0, 0}};\r
-  SendCommand(&c);\r
+       UsbCommand c = {CMD_MIFARE_SNIFFER, {0, 0, 0}};\r
+       clearCommandBuffer();\r
+       SendCommand(&c);\r
 \r
        // wait cycle\r
        while (true) {\r
@@ -1931,7 +1932,7 @@ int CmdHF14AMfSniff(const char *Cmd){
                                                sak = bufPtr[11];\r
                                                \r
                                                PrintAndLog("tag select uid:%s atqa:%02x %02x sak:0x%02x", sprint_hex(uid, 7), atqa[0], atqa[1], sak);\r
-                                               if (wantLogToFile) {\r
+                                               if (wantLogToFile || wantDecrypt) {\r
                                                        FillFileNameByUID(logHexFileName, uid, ".log", 7);\r
                                                        AddLogCurrentDT(logHexFileName);\r
                                                }                                               \r
@@ -1947,7 +1948,8 @@ int CmdHF14AMfSniff(const char *Cmd){
                        }\r
                } // resp not NILL\r
        } // while (true)\r
-  return 0;\r
+       \r
+       return 0;\r
 }\r
 \r
 static command_t CommandTable[] =\r
index f494783311398ea66fd32529687f55b09e320fb9..e773ef9326d66be61c29bc6c169be07d9703a364 100644 (file)
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ
index ec5aa75771023b75fe5b7ee0426b7aac4d5390db..3f614fdd82175805a0c6495a1b1dab32ba759f4b 100644 (file)
@@ -29,45 +29,31 @@ module hi_iso14443a(
     output dbg;
     input [2:0] mod_type;
 
-reg ssp_clk;
-reg ssp_frame;
 
-wire adc_clk;
-assign adc_clk = ck_1356meg;
+wire adc_clk = ck_1356meg;
+
 
-reg after_hysteresis, pre_after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3, after_hysteresis_prev4;
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Reader -> PM3:
+// detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a 
+// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
+reg after_hysteresis;
 reg [11:0] has_been_low_for;
-reg [8:0] saw_deep_modulation;
-reg [2:0] deep_counter;
-reg deep_modulation;
 
 always @(negedge adc_clk)
 begin
-       if(& adc_d[7:6]) after_hysteresis <= 1'b1;                      // adc_d >= 196 (U >= 3,28V) -> after_hysteris = 1
-    else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0;  // if adc_d <= 15 (U <= 1,13V) -> after_hysteresis = 0
-
-       pre_after_hysteresis <= after_hysteresis;
+       if(adc_d >= 16) after_hysteresis <= 1'b1;                       // U >= 1,14V   -> after_hysteresis = 1
+    else if(adc_d < 8) after_hysteresis <= 1'b0;               // U <  1,04V   -> after_hysteresis = 0
+       // Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit 
+       // (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
+       // In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds 
+       // 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
        
-       if(~(| adc_d[7:0]))                                                                     // if adc_d == 0 (U <= 0,94V)
-       begin
-               if(deep_counter == 3'd7)                                                // adc_d == 0 for 7 adc_clk ticks -> deep_modulation (by reader)
-               begin
-                       deep_modulation <= 1'b1;
-                       saw_deep_modulation <= 8'd0;
-               end
-               else
-                       deep_counter <= deep_counter + 1;
-       end
-       else                                                    
-       begin
-               deep_counter <= 3'd0;
-               if(saw_deep_modulation == 8'd255)                               // adc_d != 0 for 255 adc_clk ticks -> deep_modulation is over, now waiting for tag's response
-                       deep_modulation <= 1'b0;
-               else
-                       saw_deep_modulation <= saw_deep_modulation + 1;
-       end
        
-       if(after_hysteresis)
+       // detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case, 
+       // set the detected reader signal (after_hysteresis) to '1' (unmodulated)
+       if(adc_d >= 192)
     begin
         has_been_low_for <= 12'd0;
     end
@@ -76,121 +62,182 @@ begin
         if(has_been_low_for == 12'd4095)
         begin
             has_been_low_for <= 12'd0;
-            after_hysteresis <= 1'b1;                                  // reset after_hysteresis to 1 if it had been 0 for 4096 cycles (no field)
+            after_hysteresis <= 1'b1;
         end
         else
                begin
             has_been_low_for <= has_been_low_for + 1;
                end     
     end
+       
 end
 
 
 
-// Report every 4 subcarrier cycles
-// 128 periods of carrier frequency => 7-bit counter [negedge_cnt]
-reg [6:0] negedge_cnt;
-reg bit1, bit2, bit3, bit4;
-reg curbit;
-
-// storage for four previous samples:
-reg [7:0] adc_d_1;
-reg [7:0] adc_d_2;
-reg [7:0] adc_d_3;
-reg [7:0] adc_d_4;
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Reader -> PM3
+// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8 
+// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles. 
+reg deep_modulation;
+reg [2:0] deep_counter;
+reg [8:0] saw_deep_modulation;
 
-// the filtered signal (filter performs noise reduction and edge detection)
-// (gaussian derivative)
-wire signed [10:0] adc_d_filtered;
-assign adc_d_filtered = (adc_d_4 << 1) + adc_d_3 - adc_d_1 - (adc_d << 1);
+always @(negedge adc_clk)
+begin
+       if(~(| adc_d[7:0]))                                                                     // if adc_d == 0 (U <= 0,94V)
+       begin
+               if(deep_counter == 3'd7)                                                // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
+               begin
+                       deep_modulation <= 1'b1;
+                       saw_deep_modulation <= 8'd0;
+               end
+               else
+                       deep_counter <= deep_counter + 1;
+       end
+       else                                                    
+       begin
+               deep_counter <= 3'd0;
+               if(saw_deep_modulation == 8'd255)                               // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
+                       deep_modulation <= 1'b0;
+               else
+                       saw_deep_modulation <= saw_deep_modulation + 1;
+       end
+end
 
-// Registers to store steepest edges detected:
-reg [7:0] rx_mod_falling_edge_max;
-reg [7:0] rx_mod_rising_edge_max;
 
-// A register to send 8 Bit results to the arm
-reg [7:0] to_arm;
 
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Tag -> PM3
+// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
+// for noise reduction and edge detection.
+// store 4 previous samples:
+reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
+// convert to signed signals (and multiply by two for samples at t-4 and t)
+wire signed [10:0] input_prev_4_times_2 = {0, 0, input_prev_4, 0};
+wire signed [10:0] input_prev_3_times_1 = {0, 0, 0, input_prev_3};
+wire signed [10:0] input_prev_1_times_1 = {0, 0, 0, input_prev_1};
+wire signed [10:0] adc_d_times_2 = {0, 0, adc_d, 0}; 
 
-reg bit_to_arm;
-reg fdt_indicator, fdt_elapsed;
-reg [10:0] fdt_counter;
-//reg [47:0] mod_sig_buf;
-reg [31:0] mod_sig_buf;
-//reg [5:0] mod_sig_ptr;
-reg [4:0] mod_sig_ptr;
-reg [3:0] mod_sig_flip;
-reg mod_sig, mod_sig_coil;
-reg temp_buffer_reset;
-reg sendbit;
-reg [3:0] sub_carrier_cnt;
-reg[3:0] reader_falling_edge_time;
+wire signed [10:0] tmp_1, tmp_2;
+wire signed [10:0] adc_d_filtered;
+integer i;
 
-// ADC data appears on the rising edge, so sample it on the falling edge
+assign tmp_1 = input_prev_4_times_2 + input_prev_3_times_1;
+assign tmp_2 = input_prev_1_times_1 + adc_d_times_2;
+       
 always @(negedge adc_clk)
 begin
-       // ------------------------------------------------------------------------------------------------------------------------------------------------------------------
-       // relevant for TAGSIM_MOD only. Timing of Tag's answer relative to a command received from a reader
-       // ISO14443-3 specifies:
-       // fdt = 1172, if last bit was 0.
-       // fdt = 1236, if last bit was 1.
-       // the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
-       // The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
-       if(fdt_counter == 11'd547) fdt_indicator <= 1'b1;       // The ARM must not send earlier to prevent mod_sig_buf overflow.
-                                                                                                               // The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks. fdt_indicator
-                                                                                                               // could appear at ssp_din after 1 tick, 16 ticks for the transfer, 128 ticks until response is sended.
-                                                                                                               // 1148 - 464 - 1 - 128 - 8 = 547
+       // for (i = 3; i > 0; i = i - 1)
+       // begin
+               // input_shift[i] <= input_shift[i-1];
+       // end
+       // input_shift[0] <= adc_d;
+       input_prev_4 <= input_prev_3;
+       input_prev_3 <= input_prev_2;
+       input_prev_2 <= input_prev_1;
+       input_prev_1 <= adc_d;
+end    
+
+// assign adc_d_filtered = (input_shift[3] << 1) + input_shift[2] - input_shift[0] - (adc_d << 1);
+assign adc_d_filtered = tmp_1 - tmp_2;
+
        
-       if ((mod_type == `TAGSIM_MOD) || (mod_type == `TAGSIM_LISTEN))
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a 
+// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
+reg pre_after_hysteresis; 
+reg [3:0] reader_falling_edge_time;
+reg [6:0] negedge_cnt;
+
+always @(negedge adc_clk)
+begin
+       // detect a reader signal's falling edge and remember its timing:
+       pre_after_hysteresis <= after_hysteresis;
+       if (pre_after_hysteresis && ~after_hysteresis)
+       begin
+               reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
+       end
+
+       // adjust internal timer counter if necessary:
+       if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
        begin
-               if(fdt_counter == 11'd1148) // the RF part delays the rising edge by approx 5 adc_clk_ticks, the ADC needs 3 clk_ticks for A/D conversion,
-                                                                       // 16 ticks delay by mod_sig_buf
-                                                                       // 1172 - 5 - 3 - 16 = 1148.
+               if (reader_falling_edge_time == 4'd1)                   // reader signal changes right after sampling. Better sample earlier next time. 
                begin
-                       if(fdt_elapsed)
-                       begin
-                               if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig; // start modulating (if mod_sig is already set)
-                               sub_carrier_cnt[3:0] <= sub_carrier_cnt[3:0] + 1;
-                       end
-                       else
-                       begin
-                               mod_sig_flip <= negedge_cnt[3:0];                       // start modulation at this time
-                               sub_carrier_cnt[3:0] <= 0;                                      // subcarrier phase in sync with start of modulation
-                               mod_sig_coil <= mod_sig;                                        // assign signal to coil
-                               fdt_elapsed = 1'b1;
-                               if(~(| mod_sig_ptr[4:0])) mod_sig_ptr <= 5'd9;  // if mod_sig_ptr == 0 -> didn't receive a 1 yet. Delay next 1 by n*128 ticks.
-                               else temp_buffer_reset = 1'b1;                                  // else fix the buffer size at current position
-                       end
+                       negedge_cnt <= negedge_cnt + 2;                         // time warp
+               end     
+               else if (reader_falling_edge_time == 4'd0)              // reader signal changes right before sampling. Better sample later next time.
+               begin
+                       negedge_cnt <= negedge_cnt;                                     // freeze time
                end
                else
                begin
-                       fdt_counter <= fdt_counter + 1; // Count until 1155
+                       negedge_cnt <= negedge_cnt + 1;                         // Continue as usual
                end
+               reader_falling_edge_time[3:0] <= 4'd8;                  // adjust only once per detected edge
        end
-       else // other modes: don't use the delay line.
+       else if (negedge_cnt == 7'd127)                                         // normal operation: count from 0 to 127
        begin
-               mod_sig_coil <= ssp_dout;
+               negedge_cnt <= 0;
        end     
-       
-       
-       //-------------------------------------------------------------------------------------------------------------------------------------------
-       // Relevant for READER_LISTEN only
-       // look for steepest falling and rising edges:
+       else
+       begin
+               negedge_cnt <= negedge_cnt + 1;
+       end
+end    
 
-       if(negedge_cnt[3:0] == 4'd1)                                    // reset modulation detector. Save current edge.
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Tag -> PM3:
+// determine best possible time for starting/resetting the modulation detector.
+reg [3:0] mod_detect_reset_time;
+
+always @(negedge adc_clk)
+begin
+       if (mod_type == `READER_LISTEN) 
+       // (our) reader signal changes at t=1, tag response expected n*16+4 ticks later, further delayed by
+       // 3 ticks ADC conversion.
+       // 1 + 4 + 3 = 8
        begin
-               if (adc_d_filtered > 0)
-               begin
-                       rx_mod_falling_edge_max <= adc_d_filtered;
-                       rx_mod_rising_edge_max <= 0;
-               end     
-               else
+               mod_detect_reset_time <= 4'd8;
+       end
+       else
+       if (mod_type == `SNIFFER)
+       begin
+               // detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
+               if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
+               // reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed 
+               // 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
+               // The tag will respond n*16 + 4 ticks later + 3 ticks A/D converter delay.
+               // - 9 - 3 - 1 + 4 + 3 = -6
                begin
-                       rx_mod_falling_edge_max <= 0;
-                       rx_mod_rising_edge_max <= -adc_d_filtered;
+                       mod_detect_reset_time <= negedge_cnt[3:0] - 4'd4;
                end
        end
-       else                                                                                    // detect modulation
+end
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Tag -> PM3:
+// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
+// falling and rising edge (in any order), a modulation is detected.
+reg signed [10:0] rx_mod_falling_edge_max;
+reg signed [10:0] rx_mod_rising_edge_max;
+reg curbit;
+
+always @(negedge adc_clk)
+begin
+       if(negedge_cnt[3:0] == mod_detect_reset_time)
+       begin
+               // detect modulation signal: if modulating, there must have been a falling AND a rising edge
+               if (rx_mod_falling_edge_max > 5 && rx_mod_rising_edge_max > 5)
+                               curbit <= 1'b1; // modulation
+                       else
+                               curbit <= 1'b0; // no modulation
+               // reset modulation detector
+               rx_mod_rising_edge_max <= 0;
+               rx_mod_falling_edge_max <= 0;
+       end
+       else                                                                                    // look for steepest edges (slopes)
        begin
                if (adc_d_filtered > 0)
                begin
@@ -204,233 +251,309 @@ begin
                end
        end
 
-       // detect modulation signal: if modulating, there must be a falling and a rising edge
-       if (rx_mod_falling_edge_max > 6 && rx_mod_rising_edge_max > 6)
-                       curbit <= 1'b1; // modulation
-               else
-                       curbit <= 1'b0; // no modulation
-                       
-       
-       // store previous samples for filtering and edge detection:
-       adc_d_4 <= adc_d_3;
-       adc_d_3 <= adc_d_2;
-       adc_d_2 <= adc_d_1;
-       adc_d_1 <= adc_d;
+end
+
 
 
-       // Relevant for TAGSIM_MOD only (timing the Tag's answer. See above)
-       // When we see end of a modulation and we are emulating a Tag, start fdt_counter.
-       // Reset fdt_counter when modulation is detected.
-       if(~after_hysteresis /* && mod_sig_buf_empty */ && mod_type == `TAGSIM_LISTEN)
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Tag+Reader -> PM3
+// sample 4 bits reader data and 4 bits tag data for sniffing
+reg [3:0] reader_data;
+reg [3:0] tag_data;
+
+always @(negedge adc_clk)
+begin
+    if(negedge_cnt[3:0] == 4'd0)
        begin
-               fdt_counter <= 11'd0;
-               fdt_elapsed = 1'b0;
-               fdt_indicator <= 1'b0;
-               temp_buffer_reset = 1'b0;
-               mod_sig_ptr <= 5'b00000;
-               mod_sig = 1'b0;
-       end     
+        reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
+               tag_data[3:0] <= {tag_data[2:0], curbit};
+       end
+end    
+
 
 
-       if(negedge_cnt[3:0] == 4'd1)
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PM3 -> Tag:
+// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
+reg [31:0] mod_sig_buf;
+reg [4:0] mod_sig_ptr;
+reg mod_sig;
+
+always @(negedge adc_clk)
+begin
+       if(negedge_cnt[3:0] == 4'd0)    // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
        begin
-               // What do we communicate to the ARM
-               if(mod_type == `TAGSIM_LISTEN) 
-                       sendbit = after_hysteresis;
-               else if(mod_type == `TAGSIM_MOD)
-                       /* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
-                       else */ 
-                       sendbit = fdt_indicator;
-               else if (mod_type == `READER_LISTEN)
-                       sendbit = curbit;
+               mod_sig_buf[31:2] <= mod_sig_buf[30:1];                         // shift
+               if (~ssp_dout && ~mod_sig_buf[1])
+                       mod_sig_buf[1] <= 1'b0;                                                 // delete the correction bit (a single 1 preceded and succeeded by 0)
                else
-                       sendbit = 1'b0;
+                       mod_sig_buf[1] <= mod_sig_buf[0];
+               mod_sig_buf[0] <= ssp_dout;                                                     // add new data to the delay line
+
+               mod_sig = mod_sig_buf[mod_sig_ptr];                                     // the delayed signal.
        end
+end
 
 
 
-       // check timing of a falling edge in reader signal
-       if (pre_after_hysteresis && ~after_hysteresis)
-               reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PM3 -> Tag, internal timing:
+// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
+// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
+// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
+// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the 
+// transmission stream, causing the required additional delay.
+reg [10:0] fdt_counter;
+reg fdt_indicator, fdt_elapsed;
+reg [3:0] mod_sig_flip;
+reg [3:0] sub_carrier_cnt;
 
+// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
+// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
+// count to 1172 - 9 - 3 - 32 = 1128
+`define FDT_COUNT 11'd1128
 
+// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
+// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
+// fdt_indicator could appear at ssp_din after 1 tick, the transfer needs 16 ticks, the ARM can send 128 ticks later.
+// 1128 - 464 - 1 - 128 - 8 = 535
+`define FDT_INDICATOR_COUNT 11'd535
 
-       // sync clock to external reader's clock:
-       if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_MOD || mod_type == `TAGSIM_LISTEN))
+// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
+assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
+
+always @(negedge adc_clk)
+begin
+       if (fdt_reset)
        begin
-               // adjust clock if necessary:
-               if (reader_falling_edge_time < 4'd8 && reader_falling_edge_time > 4'd1)
-               begin
-                       negedge_cnt <= negedge_cnt;                             // freeze time
+               fdt_counter <= 11'd0;
+               fdt_elapsed <= 1'b0;
+               fdt_indicator <= 1'b0;
+       end     
+       else
+       begin
+               if(fdt_counter == `FDT_COUNT)
+               begin                                           
+                       if(~fdt_elapsed)                                                        // just reached fdt.
+                       begin
+                               mod_sig_flip <= negedge_cnt[3:0];               // start modulation at this time
+                               sub_carrier_cnt <= 4'd0;                                // subcarrier phase in sync with start of modulation
+                               fdt_elapsed <= 1'b1;
+                       end
+                       else
+                       begin
+                               sub_carrier_cnt <= sub_carrier_cnt + 1;
+                       end     
                end     
-               else if (reader_falling_edge_time == 4'd8)
-               begin
-                       negedge_cnt <= negedge_cnt + 1;                 // the desired state. Advance as usual;
-               end
                else
                begin
-                       negedge_cnt[3:0] <= 4'd15;                              // time warp
+                       fdt_counter <= fdt_counter + 1;
                end
-               reader_falling_edge_time <= 4'd8;                       // only once per detected rising edge
        end
        
+       if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
+end
+
 
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PM3 -> Reader or Tag
+// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
+// or undelayed when sending to a tag
+reg mod_sig_coil;
 
-       //------------------------------------------------------------------------------------------------------------------------------------------
-       // Prepare 8 Bits to communicate to ARM
-       if (negedge_cnt == 7'd63)
+always @(negedge adc_clk)
+begin
+       if (mod_type == `TAGSIM_MOD)                     // need to take care of proper fdt timing
        begin
-               if (mod_type == `SNIFFER)
+               if(fdt_counter == `FDT_COUNT)
                begin
-                       if(deep_modulation) // a reader is sending (or there's no field at all)
+                       if(fdt_elapsed)
                        begin
-                               to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,1'b0,1'b0,1'b0,1'b0};
+                               if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
                        end
                        else
                        begin
-                               to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,bit1,bit2,bit3,bit4};
-                       end                     
-                       negedge_cnt <= 0;
+                               mod_sig_coil <= mod_sig;        // just reached fdt. Immediately assign signal to coil
+                       end
                end
-               else
+       end
+       else                                                                    // other modes: don't delay
+       begin
+               mod_sig_coil <= ssp_dout;
+       end     
+end
+
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PM3 -> Reader
+// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
+reg temp_buffer_reset;
+
+always @(negedge adc_clk)
+begin
+       if(fdt_reset)
+       begin
+               mod_sig_ptr <= 5'd0;
+               temp_buffer_reset = 1'b0;
+       end     
+       else
+       begin
+               if(fdt_counter == `FDT_COUNT && ~fdt_elapsed)                                                   // if we just reached fdt
+                       if(~(| mod_sig_ptr[4:0])) 
+                               mod_sig_ptr <= 5'd8;                                                                                    // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
+                       else 
+                               temp_buffer_reset = 1'b1;                                                                               // else no need for further delays.
+
+               if(negedge_cnt[3:0] == 4'd0)                                                                                    // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
                begin
-                       negedge_cnt <= negedge_cnt + 1;
+                       if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed)                          // buffer a 1 (and all subsequent data) until fdt is reached.
+                               if (mod_sig_ptr == 5'd31) 
+                                       mod_sig_ptr <= 5'd0;                                                                            // buffer overflow - data loss.
+                               else 
+                                       mod_sig_ptr <= mod_sig_ptr + 1;                                                         // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
+                       else if(fdt_elapsed && ~temp_buffer_reset)                                                      
+                       begin
+                               // wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
+                               // at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
+                               if(ssp_dout) 
+                                       temp_buffer_reset = 1'b1;                                                       
+                               if(mod_sig_ptr == 5'd1) 
+                                       mod_sig_ptr <= 5'd8;                                                                            // still nothing received, need to go for the next interval
+                               else 
+                                       mod_sig_ptr <= mod_sig_ptr - 1;                                                         // decrease buffer.
+                       end
                end
-       end     
-       else if(negedge_cnt == 7'd127)
+       end
+end
+
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// FPGA -> ARM communication:
+// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
+reg [7:0] to_arm;
+
+always @(negedge adc_clk)
+begin
+       if (negedge_cnt[5:0] == 6'd63)                                                  // fill the buffer
        begin
-               if (mod_type == `TAGSIM_MOD)
+               if (mod_type == `SNIFFER)
                begin
-                       to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]};
-                       negedge_cnt <= 0;
+                       if(deep_modulation)                                                     // a reader is sending (or there's no field at all)
+                       begin
+                               to_arm <= {reader_data[3:0], 4'b0000};          // don't send tag data
+                       end
+                       else
+                       begin
+                               to_arm <= {reader_data[3:0], tag_data[3:0]};
+                       end                     
                end
                else
                begin
-                       to_arm[7:0] <= 8'd0;
-                       negedge_cnt <= negedge_cnt + 1;
+                       to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
                end
-       end
-       else
-       begin
-               negedge_cnt <= negedge_cnt + 1;
-       end
+       end     
 
-       
-    if(negedge_cnt == 7'd1)
-       begin
-        after_hysteresis_prev1 <= after_hysteresis;
-               bit1 <= curbit;
-       end
-    if(negedge_cnt == 7'd17)
+       if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER)  // shift at double speed
        begin
-        after_hysteresis_prev2 <= after_hysteresis;
-               bit2 <= curbit;
-       end
-    if(negedge_cnt == 7'd33)
-       begin
-        after_hysteresis_prev3 <= after_hysteresis;
-               bit3 <= curbit;
-       end
-    if(negedge_cnt == 7'd49)
-       begin
-        after_hysteresis_prev4 <= after_hysteresis;
-               bit4 <= curbit;
-       end
-       
-       //--------------------------------------------------------------------------------------------------------------------------------------------------------------
-       // Relevant in TAGSIM_MOD only. Delay-Line to buffer data and send it at the correct time
-       if(negedge_cnt[3:0] == 4'd0)    // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
-       begin
-               mod_sig_buf[31:0] <= {mod_sig_buf[30:1], ssp_dout, 1'b0};                       // shift in new data starting at mod_sig_buf[1]. mod_sig_buf[0] = 0 always.
-               // asign the delayed signal to mod_sig, but don't modulate with the correction bit (which is sent as 00010000, all other bits will come with at least 2 consecutive 1s)
-               // side effect: when ptr = 1 it will cancel the first 1 of every block of ones. Note: this would only be the case if we received a 1 just before fdt_elapsed.
-               if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed)                          // buffer a 1 (and all subsequent data) until fdt_counter = 1148 adc_clk ticks.
-                       //if(mod_sig_ptr == 6'b101110)                                                                  // buffer overflow at 46 - this would mean data loss
-                       //begin
-                       //      mod_sig_ptr <= 6'b000000;
-                       //end
-                       if (mod_sig_ptr == 5'd30) mod_sig_ptr <= 5'd0;
-                       else mod_sig_ptr <= mod_sig_ptr + 1;                                                    // increase buffer (= increase delay by 16 adc_clk ticks). ptr always points to first 1.
-               else if(fdt_elapsed && ~temp_buffer_reset)                                                      
-               // fdt_elapsed. If we didn't receive a 1 yet, ptr will be at 9 and not yet fixed. Otherwise temp_buffer_reset will be 1 already.
+               // Don't shift if we just loaded new data, obviously.
+               if(negedge_cnt[5:0] != 6'd0)
                begin
-                       // wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
-                       // at intervals of 8 * 16 = 128 adc_clk ticks intervals (as defined in ISO14443-3)
-                       if(ssp_dout) temp_buffer_reset = 1'b1;                                                  
-                       if(mod_sig_ptr == 5'd2) mod_sig_ptr <= 5'd9;                                    // still nothing received, need to go for the next interval
-                       else mod_sig_ptr <= mod_sig_ptr - 1;                                                    // decrease buffer.
+                       to_arm[7:1] <= to_arm[6:0];
                end
-               else
+       end
+
+       if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
+       begin
+               // Don't shift if we just loaded new data, obviously.
+               if(negedge_cnt[6:0] != 7'd0)
                begin
-                       if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
-                       // finally, assign the delayed signal:
-                       else mod_sig = mod_sig_buf[mod_sig_ptr];
+                       to_arm[7:1] <= to_arm[6:0];
                end
        end
        
-       //-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-       // Communication to ARM (SSP Clock and data)
-       // SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
+end
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// FPGA -> ARM communication:
+// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
+reg ssp_clk;
+reg ssp_frame;
+reg [2:0] ssp_frame_counter;
+
+always @(negedge adc_clk)
+begin
        if(mod_type == `SNIFFER)
+       // SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
        begin
-               if(negedge_cnt[2:0] == 3'b100)
-                       ssp_clk <= 1'b0;
-                       
-               if(negedge_cnt[2:0] == 3'b000)
-               begin
+               if(negedge_cnt[2:0] == 3'd0)
                        ssp_clk <= 1'b1;
-                       // Don't shift if we just loaded new data, obviously.
-                       if(negedge_cnt[5:0] != 6'd0)
-                       begin
-                               to_arm[7:1] <= to_arm[6:0];
-                       end
-               end
+               if(negedge_cnt[2:0] == 3'd4)
+                       ssp_clk <= 1'b0;
 
-               if(negedge_cnt[5:4] == 2'b00)
-                       ssp_frame = 1'b1;
-               else
-                       ssp_frame = 1'b0;
-               
-               bit_to_arm = to_arm[7];
+               if(negedge_cnt[5:0] == 6'd0)    // ssp_frame rising edge indicates start of frame
+                       ssp_frame <= 1'b1;
+               if(negedge_cnt[5:0] == 6'd8)    
+                       ssp_frame <= 1'b0;
        end
        else
-       //-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-       // Communication to ARM (SSP Clock and data)
        // all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
        begin
-               if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
+               if(negedge_cnt[3:0] == 4'd0)
+                       ssp_clk <= 1'b1;
+               if(negedge_cnt[3:0] == 4'd8) 
+                       ssp_clk <= 1'b0;
 
-               if(negedge_cnt[3:0] == 4'b0111)
-               begin
-                       // if(ssp_frame_counter == 3'd7) ssp_frame_counter <= 3'd0;
-                       // else ssp_frame_counter <= ssp_frame_counter + 1;
-                       if (negedge_cnt[6:4] == 3'b000) ssp_frame = 1'b1;
-                       else ssp_frame = 1'b0;
-               end
-               // ssp_frame = (ssp_frame_counter == 3'd7);
+               if(negedge_cnt[6:0] == 7'd7)    // ssp_frame rising edge indicates start of frame
+                       ssp_frame <= 1'b1;
+               if(negedge_cnt[6:0] == 7'd23)
+                       ssp_frame <= 1'b0;
+       end     
+end
 
-               if(negedge_cnt[3:0] == 4'b0000)
-               begin
-                       ssp_clk <= 1'b1;
-                       // Don't shift if we just loaded new data, obviously.
-                       if(negedge_cnt[6:0] != 7'd0)
-                       begin
-                               to_arm[7:1] <= to_arm[6:0];
-                       end
-               end
-               
-               if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
-                       // transmit timing information
-                       bit_to_arm = to_arm[7];
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// FPGA -> ARM communication:
+// select the data to be sent to ARM
+reg bit_to_arm;
+reg sendbit;
+
+always @(negedge adc_clk)
+begin
+       if(negedge_cnt[3:0] == 4'd0)
+       begin
+               // What do we communicate to the ARM
+               if(mod_type == `TAGSIM_LISTEN) 
+                       sendbit = after_hysteresis;
+               else if(mod_type == `TAGSIM_MOD)
+                       /* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
+                       else */ 
+                       sendbit = fdt_indicator;
+               else if (mod_type == `READER_LISTEN)
+                       sendbit = curbit;
                else
-                       // transmit data or fdt_indicator
-                       bit_to_arm = sendbit;
-               end
-       
-end    //always @(negedge adc_clk)
+                       sendbit = 1'b0;
+       end
 
-assign ssp_din = bit_to_arm;
 
+       if(mod_type == `SNIFFER)
+               // send sampled reader and tag data:
+               bit_to_arm = to_arm[7];
+       else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
+               // send timing information:
+               bit_to_arm = to_arm[7];
+       else
+               // send data or fdt_indicator
+               bit_to_arm = sendbit;
+end
+
+
+
+
+assign ssp_din = bit_to_arm;
 
 // Subcarrier (adc_clk/16, for TAGSIM_MOD only).
 wire sub_carrier;
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