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2 | -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. | |
3 | -------------------------------------------------------------------------------- | |
4 | -- ____ ____ | |
5 | -- / /\/ / | |
6 | -- /___/ \ / Vendor: Xilinx | |
7 | -- \ \ \/ Version : 9.1.02i | |
8 | -- \ \ Application : xaw2vhdl | |
9 | -- / / Filename : phydcm.vhd | |
10 | -- /___/ /\ Timestamp : 03/21/2007 14:47:39 | |
11 | -- \ \ / \ | |
12 | -- \___\/\___\ | |
13 | -- | |
14 | --Command: xaw2vhdl-st phydcm.xaw phydcm | |
15 | --Design Name: phydcm | |
16 | --Device: xc3s1500-fg456-4 | |
17 | -- | |
18 | -- Module phydcm | |
19 | -- Generated by Xilinx Architecture Wizard | |
20 | -- Written for synthesis tool: XST | |
21 | ||
22 | library ieee; | |
23 | use ieee.std_logic_1164.ALL; | |
24 | use ieee.numeric_std.ALL; | |
25 | library UNISIM; | |
26 | use UNISIM.Vcomponents.ALL; | |
27 | ||
28 | entity phydcm is | |
29 | port ( CLKIN_IN : in std_logic; | |
30 | RST_IN : in std_logic; | |
31 | CLKFX_OUT : out std_logic; | |
32 | CLKIN_IBUFG_OUT : out std_logic; | |
33 | CLK0_OUT : out std_logic; | |
34 | LOCKED_OUT : out std_logic); | |
35 | end phydcm; | |
36 | ||
37 | architecture BEHAVIORAL of phydcm is | |
38 | signal CLKFB_IN : std_logic; | |
39 | signal CLKFX_BUF : std_logic; | |
40 | signal CLKIN_IBUFG : std_logic; | |
41 | signal CLK0_BUF : std_logic; | |
42 | signal GND_BIT : std_logic; | |
43 | component BUFG | |
44 | port ( I : in std_logic; | |
45 | O : out std_logic); | |
46 | end component; | |
47 | ||
48 | component IBUFG | |
49 | port ( I : in std_logic; | |
50 | O : out std_logic); | |
51 | end component; | |
52 | ||
53 | -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI | |
54 | -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns | |
55 | component DCM | |
56 | generic( CLK_FEEDBACK : string := "1X"; | |
57 | CLKDV_DIVIDE : real := 2.0; | |
58 | CLKFX_DIVIDE : integer := 1; | |
59 | CLKFX_MULTIPLY : integer := 4; | |
60 | CLKIN_DIVIDE_BY_2 : boolean := FALSE; | |
61 | CLKIN_PERIOD : real := 10.0; | |
62 | CLKOUT_PHASE_SHIFT : string := "NONE"; | |
63 | DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; | |
64 | DFS_FREQUENCY_MODE : string := "LOW"; | |
65 | DLL_FREQUENCY_MODE : string := "LOW"; | |
66 | DUTY_CYCLE_CORRECTION : boolean := TRUE; | |
67 | FACTORY_JF : bit_vector := x"C080"; | |
68 | PHASE_SHIFT : integer := 0; | |
69 | STARTUP_WAIT : boolean := FALSE; | |
70 | DSS_MODE : string := "NONE"); | |
71 | port ( CLKIN : in std_logic; | |
72 | CLKFB : in std_logic; | |
73 | RST : in std_logic; | |
74 | PSEN : in std_logic; | |
75 | PSINCDEC : in std_logic; | |
76 | PSCLK : in std_logic; | |
77 | DSSEN : in std_logic; | |
78 | CLK0 : out std_logic; | |
79 | CLK90 : out std_logic; | |
80 | CLK180 : out std_logic; | |
81 | CLK270 : out std_logic; | |
82 | CLKDV : out std_logic; | |
83 | CLK2X : out std_logic; | |
84 | CLK2X180 : out std_logic; | |
85 | CLKFX : out std_logic; | |
86 | CLKFX180 : out std_logic; | |
87 | STATUS : out std_logic_vector (7 downto 0); | |
88 | LOCKED : out std_logic; | |
89 | PSDONE : out std_logic); | |
90 | end component; | |
91 | ||
92 | begin | |
93 | GND_BIT <= '0'; | |
94 | CLKIN_IBUFG_OUT <= CLKIN_IBUFG; | |
95 | CLK0_OUT <= CLKFB_IN; | |
96 | CLKFX_BUFG_INST : BUFG | |
97 | port map (I=>CLKFX_BUF, | |
98 | O=>CLKFX_OUT); | |
99 | ||
100 | CLKIN_IBUFG_INST : IBUFG | |
101 | port map (I=>CLKIN_IN, | |
102 | O=>CLKIN_IBUFG); | |
103 | ||
104 | CLK0_BUFG_INST : BUFG | |
105 | port map (I=>CLK0_BUF, | |
106 | O=>CLKFB_IN); | |
107 | ||
108 | DCM_INST : DCM | |
109 | generic map( CLK_FEEDBACK => "1X", | |
110 | CLKDV_DIVIDE => 2.0, | |
111 | CLKFX_DIVIDE => 29, | |
112 | CLKFX_MULTIPLY => 22, | |
113 | CLKIN_DIVIDE_BY_2 => FALSE, | |
114 | CLKIN_PERIOD => 30.303, | |
115 | CLKOUT_PHASE_SHIFT => "NONE", | |
116 | DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", | |
117 | DFS_FREQUENCY_MODE => "LOW", | |
118 | DLL_FREQUENCY_MODE => "LOW", | |
119 | DUTY_CYCLE_CORRECTION => TRUE, | |
120 | FACTORY_JF => x"8080", | |
121 | PHASE_SHIFT => 0, | |
122 | STARTUP_WAIT => FALSE) | |
123 | port map (CLKFB=>CLKFB_IN, | |
124 | CLKIN=>CLKIN_IBUFG, | |
125 | DSSEN=>GND_BIT, | |
126 | PSCLK=>GND_BIT, | |
127 | PSEN=>GND_BIT, | |
128 | PSINCDEC=>GND_BIT, | |
129 | RST=>RST_IN, | |
130 | CLKDV=>open, | |
131 | CLKFX=>CLKFX_BUF, | |
132 | CLKFX180=>open, | |
133 | CLK0=>CLK0_BUF, | |
134 | CLK2X=>open, | |
135 | CLK2X180=>open, | |
136 | CLK90=>open, | |
137 | CLK180=>open, | |
138 | CLK270=>open, | |
139 | LOCKED=>LOCKED_OUT, | |
140 | PSDONE=>open, | |
141 | STATUS=>open); | |
142 | ||
143 | end BEHAVIORAL; | |
144 | ||
145 |