3 use ieee.std_logic_1164.all;
4 use ieee.std_logic_unsigned.all;
8 divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
13 nrst_i : in std_logic;
14 led2_o : out std_logic;
15 led3_o : out std_logic;
16 led4_o : out std_logic;
17 led5_o : out std_logic;
18 led6_o : out std_logic;
19 led7_o : out std_logic;
20 led8_o : out std_logic;
21 led9_o : out std_logic
26 architecture rtl of heartbeat is
29 process(clk_i, nrst_i)
30 variable counter : std_logic_vector(31 downto 0);
31 variable state : std_logic_vector(7 downto 0) := "00000001";
32 variable direction : std_logic := '0';
35 if (rising_edge(clk_i)) then
37 counter := (others => '0');
47 counter := counter + 1;
48 if counter = divider then
49 if state(7) = '1' then
53 if state(0) = '1' then
57 if direction = '0' then
58 state(7 downto 1) := state(6 downto 0);
61 state(6 downto 0) := state(7 downto 1);
64 counter := (others => '0');