7 use ieee.std_logic_1164.all;
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 PCI_FRAMEn :in std_logic;
15 PCI_IRDYn :in std_logic;
16 PCI_IDSEL :in std_logic;
17 PCI_PAR :in std_logic;
18 PCI_CBEn :in std_logic_vector ( 3 downto 0);
19 OE_PCI_AD :in std_logic;
20 IO_DATA :in std_logic_vector (31 downto 0);
21 AD_REG :out std_logic_vector (31 downto 0);
22 CBE_REGn :out std_logic_vector ( 3 downto 0);
23 FRAME_REGn :out std_logic;
24 IRDY_REGn :out std_logic;
25 IDSEL_REG :out std_logic;
26 PAR_REG :out std_logic;
27 PCI_AD :out std_logic_vector (31 downto 0) -- t/s
31 architecture IO_REG_DESIGN of IO_REG is
33 signal REG_AD :std_logic_vector (31 downto 0);
34 signal REG_CBEn :std_logic_vector ( 3 downto 0);
35 signal REG_FRAMEn :std_logic;
36 signal REG_IRDYn :std_logic;
37 signal REG_IDSEL :std_logic;
38 signal REG_PAR :std_logic;
42 process (PCI_CLOCK, PCI_RSTn)
44 if PCI_RSTn = '0' then
46 REG_AD <= X"00000000";
53 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
57 REG_FRAMEn <= PCI_FRAMEn;
58 REG_IRDYn <= PCI_IRDYn;
59 REG_IDSEL <= PCI_IDSEL;
65 PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
69 FRAME_REGn <= REG_FRAMEn;
70 IRDY_REGn <= REG_IRDYn;
71 IDSEL_REG <= REG_IDSEL;
74 end architecture IO_REG_DESIGN;