1 -- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $
4 use IEEE.std_logic_1164.all;
6 entity FIFO_IO_CONTROL is
9 PCI_CLOCK :in std_logic;
10 WRITE_XX1_0 :in std_logic; -- PCI Write
11 FIFO_RDn :in std_logic; -- FIFO Read (low active)
13 SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
14 SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
15 S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
16 R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
17 S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
18 R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
19 S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
20 R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
21 S_ERROR :out std_logic; -- Send ERROR
22 R_ERROR :out std_logic; -- Recv ERROR
23 SR_ERROR :out std_logic -- Send / Recv Error
25 end entity FIFO_IO_CONTROL;
27 architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
29 signal SIG_S_ERROR :std_logic; -- Send Error
30 signal SIG_R_ERROR :std_logic; -- Recv Error
38 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
43 elsif (WRITE_XX1_0 = '0') then
46 elsif (WRITE_XX1_0 = '1') then
47 if (SYNC_FLAG_7 = '0') then
50 elsif (SYNC_FLAG_7 = '1') then
58 S_ERROR <= SIG_S_ERROR;
62 R_FIFO_READn <= FIFO_RDn;
68 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
72 elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
78 R_ERROR <= SIG_R_ERROR;
80 -- Send or Receive Error
84 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
85 SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
93 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
94 S_FIFO_RESETn <= not RESET;
95 R_FIFO_RESETn <= not RESET;
104 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
105 S_FIFO_RETRANSMITn <= '1';
106 R_FIFO_RETRANSMITn <= '1';
110 end architecture FIFO_IO_CONTROL_DESIGN;