1 //////////////////////////////////////////////////////////////////////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
11 //// All additional information is avaliable in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2001, 2002 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
41 // CVS Revision History
43 // $Log: eth_cop.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
47 // Revision 1.4 2003/06/13 11:55:37 mohor
48 // Define file in eth_cop.v is changed to eth_defines.v. Some defines were
49 // moved from tb_eth_defines.v to eth_defines.v.
51 // Revision 1.3 2002/10/10 16:43:59 mohor
52 // Minor $display change.
54 // Revision 1.2 2002/09/09 12:54:13 mohor
55 // error acknowledge cycle termination added to display.
57 // Revision 1.1 2002/08/14 17:16:07 mohor
58 // Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
60 // - Host connects to the master interface
61 // - Ethernet master (DMA) connects to the second master interface
62 // - Memory interface connects to the slave interface
63 // - Ethernet slave interface (access to registers and BDs) connects to second
71 `include "eth_defines.v"
72 `include "timescale.v"
80 m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
81 m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
85 m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
86 m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
90 s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
91 s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
95 s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
96 s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
103 input wb_clk_i, wb_rst_i;
106 input [31:0] m1_wb_adr_i, m1_wb_dat_i;
107 input [3:0] m1_wb_sel_i;
108 input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
109 output [31:0] m1_wb_dat_o;
110 output m1_wb_ack_o, m1_wb_err_o;
113 input [31:0] m2_wb_adr_i, m2_wb_dat_i;
114 input [3:0] m2_wb_sel_i;
115 input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
116 output [31:0] m2_wb_dat_o;
117 output m2_wb_ack_o, m2_wb_err_o;
120 input [31:0] s1_wb_dat_i;
121 input s1_wb_ack_i, s1_wb_err_i;
122 output [31:0] s1_wb_adr_o, s1_wb_dat_o;
123 output [3:0] s1_wb_sel_o;
124 output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
127 input [31:0] s2_wb_dat_i;
128 input s2_wb_ack_i, s2_wb_err_i;
129 output [31:0] s2_wb_adr_o, s2_wb_dat_o;
130 output [3:0] s2_wb_sel_o;
131 output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
135 reg [31:0] s1_wb_adr_o;
136 reg [3:0] s1_wb_sel_o;
138 reg [31:0] s1_wb_dat_o;
141 reg [31:0] s2_wb_adr_o;
142 reg [3:0] s2_wb_sel_o;
144 reg [31:0] s2_wb_dat_o;
149 reg [31:0] m1_wb_dat_o;
151 reg [31:0] m2_wb_dat_o;
156 wire m_wb_access_finished;
157 wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
158 wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
160 always @ (posedge wb_clk_i or posedge wb_rst_i)
164 m1_in_progress <=#Tp 0;
165 m2_in_progress <=#Tp 0;
181 case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
182 5'b00_10_0, 5'b00_11_0 :
184 m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
187 s1_wb_adr_o <=#Tp m1_wb_adr_i;
188 s1_wb_sel_o <=#Tp m1_wb_sel_i;
189 s1_wb_we_o <=#Tp m1_wb_we_i;
190 s1_wb_dat_o <=#Tp m1_wb_dat_i;
191 s1_wb_cyc_o <=#Tp 1'b1;
192 s1_wb_stb_o <=#Tp 1'b1;
194 else if(`M1_ADDRESSED_S2)
196 s2_wb_adr_o <=#Tp m1_wb_adr_i;
197 s2_wb_sel_o <=#Tp m1_wb_sel_i;
198 s2_wb_we_o <=#Tp m1_wb_we_i;
199 s2_wb_dat_o <=#Tp m1_wb_dat_i;
200 s2_wb_cyc_o <=#Tp 1'b1;
201 s2_wb_stb_o <=#Tp 1'b1;
204 $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
208 m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
211 s1_wb_adr_o <=#Tp m2_wb_adr_i;
212 s1_wb_sel_o <=#Tp m2_wb_sel_i;
213 s1_wb_we_o <=#Tp m2_wb_we_i;
214 s1_wb_dat_o <=#Tp m2_wb_dat_i;
215 s1_wb_cyc_o <=#Tp 1'b1;
216 s1_wb_stb_o <=#Tp 1'b1;
218 else if(`M2_ADDRESSED_S2)
220 s2_wb_adr_o <=#Tp m2_wb_adr_i;
221 s2_wb_sel_o <=#Tp m2_wb_sel_i;
222 s2_wb_we_o <=#Tp m2_wb_we_i;
223 s2_wb_dat_o <=#Tp m2_wb_dat_i;
224 s2_wb_cyc_o <=#Tp 1'b1;
225 s2_wb_stb_o <=#Tp 1'b1;
228 $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
230 5'b10_10_1, 5'b10_11_1 :
232 m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
235 s1_wb_cyc_o <=#Tp 1'b0;
236 s1_wb_stb_o <=#Tp 1'b0;
238 else if(`M1_ADDRESSED_S2)
240 s2_wb_cyc_o <=#Tp 1'b0;
241 s2_wb_stb_o <=#Tp 1'b0;
244 5'b01_01_1, 5'b01_11_1 :
246 m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
249 s1_wb_cyc_o <=#Tp 1'b0;
250 s1_wb_stb_o <=#Tp 1'b0;
252 else if(`M2_ADDRESSED_S2)
254 s2_wb_cyc_o <=#Tp 1'b0;
255 s2_wb_stb_o <=#Tp 1'b0;
262 // Generating Ack for master 1
263 always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
267 if(`M1_ADDRESSED_S1) begin
268 m1_wb_ack_o <= s1_wb_ack_i;
269 m1_wb_dat_o <= s1_wb_dat_i;
271 else if(`M1_ADDRESSED_S2) begin
272 m1_wb_ack_o <= s2_wb_ack_i;
273 m1_wb_dat_o <= s2_wb_dat_i;
281 // Generating Ack for master 2
282 always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
286 if(`M2_ADDRESSED_S1) begin
287 m2_wb_ack_o <= s1_wb_ack_i;
288 m2_wb_dat_o <= s1_wb_dat_i;
290 else if(`M2_ADDRESSED_S2) begin
291 m2_wb_ack_o <= s2_wb_ack_i;
292 m2_wb_dat_o <= s2_wb_dat_i;
300 // Generating Err for master 1
301 always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
302 m1_wb_cyc_i or m1_wb_stb_i)
304 if(m1_in_progress) begin
306 m1_wb_err_o <= s1_wb_err_i;
307 else if(`M1_ADDRESSED_S2)
308 m1_wb_err_o <= s2_wb_err_i;
310 else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
317 // Generating Err for master 2
318 always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
319 m2_wb_cyc_i or m2_wb_stb_i)
321 if(m2_in_progress) begin
323 m2_wb_err_o <= s1_wb_err_i;
324 else if(`M2_ADDRESSED_S2)
325 m2_wb_err_o <= s2_wb_err_i;
327 else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
334 assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
339 always @ (posedge wb_clk_i or posedge wb_rst_i)
344 if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
347 if(s1_wb_cyc_o | s2_wb_cyc_o)
351 always @ (posedge wb_clk_i)
354 $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
355 if(s1_wb_cyc_o) begin
356 $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
357 $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
358 $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
359 $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
361 else if(s2_wb_cyc_o) begin
362 $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
363 $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
364 $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
365 $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
373 always @ (posedge wb_clk_i)
375 if(s1_wb_err_i & s1_wb_cyc_o) begin
376 $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
377 $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
378 $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
379 $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
380 $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
383 if(s2_wb_err_i & s2_wb_cyc_o) begin
384 $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
385 $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
386 $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
387 $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
388 $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);