git.zerfleddert.de Git - raggedstone/blob - dhwk/source/COMM_DEC.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: COMM_DEC.VHD
   5
   6 library ieee;
   7 use ieee.std_logic_1164.all ;
   8
   9 entity COMM_DEC is
  10         port
  11         (
  12         PCI_CLOCK               :in             std_logic;
  13         PCI_RSTn                :in             std_logic;
  14         MY_ADDR                 :in             std_logic;
  15         IDSEL_REG               :in             std_logic;
  16         FRAME_REGn      :in             std_logic;
  17         IO_SPACE                :in             std_logic;
  18         AD_REG                  :in             std_logic_vector(31 downto 0);
  19         CBE_REGn                :in             std_logic_vector( 3 downto 0);
  20         LAR                                     :out    std_logic;--LOAD_ADDR_REG
  21         IO_READ                 :out    std_logic;
  22         IO_WRITE                :out    std_logic;
  23         CONF_READ               :out    std_logic;
  24         CONF_WRITE      :out    std_logic;
  25         SERR_CHECK      :out    std_logic
  26         );
  27 end entity COMM_DEC ;
  28
  29 architecture COMM_DEC_DESIGN of COMM_DEC is
  30
  31
  32 --PCI Bus Commands
  33 --C/BE[3..0] Command Type
  34 --------------------------------------
  35 --      0000            Interrupt Acknowledge
  36 --      0001            Special Cycle
  37 --      0010            I/O Read
  38 --      0011            I/O Write
  39 --      0100            Reserved
  40 --      0101            Reserved
  41 --      0110            Memory Read
  42 --      0111            Memory Write
  43 --
  44 --      1000            Reserved
  45 --      1001            Reserved
  46 --      1010            Configuration Read
  47 --      1011            Configuration Write
  48 --      1100            Memory Read Multiple
  49 --      1101            Dual Address Cycle
  50 --      1110            Memory Read Line
  51 --      1111            Memory Write and Invalidate
  52
  53
  54 --PCI Byte Enable
  55 --C/BE[3..0] gueltige Datenbits
  56 -------------------------------
  57 --      0000            AD 31..0
  58 --      1000            AD 23..0
  59 --      1100            AD 15..0
  60 --      1110            AD  7..0
  61
  62         constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";
  63         constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";
  64         constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";
  65         constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";
  66         constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";
  67         constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";
  68         constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";
  69         constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";
  70         constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";
  71         constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";
  72         constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";
  73         constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";
  74         constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";
  75         constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";
  76         constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";
  77         constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";
  78
  79         signal          START                                           :std_logic;
  80         signal          FRAME_REG_REGn  :std_logic;
  81
  82         signal          SIG_IO_READ                     :std_logic;
  83         signal          SIG_IO_WRITE            :std_logic;
  84         signal          SIG_CONF_READ           :std_logic;
  85         signal          SIG_CONF_WRITE  :std_logic;
  86
  87 begin
  88
  89         process (PCI_CLOCK, PCI_RSTn)
  90         begin
  91                 if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';
  92                 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
  93
  94                         FRAME_REG_REGn  <=      FRAME_REGn;
  95
  96                 end if;
  97         end process;
  98
  99
 100         START                   <= (not FRAME_REGn) and FRAME_REG_REGn;
 101
 102
 103
 104         SIG_IO_READ             <= '1'  when    START                   = '1'
 105                                                                                                 and             IO_SPACE        = '1'
 106                                                                                                 and             CBE_REGn        = cmd_io_read
 107                                                                                                 and             MY_ADDR         = '1'
 108                                                         else '0';
 109
 110
 111         SIG_IO_WRITE    <= '1'  when    START                   = '1'
 112                                                                                                 and             IO_SPACE        = '1'
 113                                                                                                 and             CBE_REGn        = cmd_io_write
 114                                                                                                 and             MY_ADDR         = '1'
 115                                                         else '0';
 116
 117
 118         SIG_CONF_READ   <= '1'  when    START                                                           = '1'
 119                                                                                                 and             AD_REG(1 downto 0)      = "00"
 120                                                                                                 and             CBE_REGn                                                = cmd_conf_read
 121                                                                                                 and             IDSEL_REG                                               = '1'
 122
 123                                                 else '0';
 124
 125
 126         SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'
 127                                                                                                         and             AD_REG(1 downto 0)      = "00"
 128                                                                                                         and             CBE_REGn                                                = cmd_conf_write
 129                                                                                                         and             IDSEL_REG                                               = '1'
 130                                                                 else '0';
 131
 132         LAR                     <=      START;
 133
 134         SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;
 135
 136         IO_READ         <=      SIG_IO_READ;
 137         IO_WRITE        <=      SIG_IO_WRITE;
 138         CONF_READ         <=    SIG_CONF_READ;
 139         CONF_WRITE      <=      SIG_CONF_WRITE;
 140
 141 end architecture COMM_DEC_DESIGN ;