1 //////////////////////////////////////////////////////////////////////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
11 //// All additional information is available in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2001, 2002 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
41 // CVS Revision History
43 // $Log: eth_top.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
47 // Revision 1.52 2005/03/21 20:07:18 igorm
48 // Some small fixes + some troubles fixed.
50 // Revision 1.51 2005/02/21 11:13:17 igorm
51 // Defer indication fixed.
53 // Revision 1.50 2004/04/26 15:26:23 igorm
54 // - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
55 // previous update of the core.
56 // - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
57 // - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
58 // register. (thanks to Mathias and Torbjorn)
59 // - Multicast reception was fixed. Thanks to Ulrich Gries
61 // Revision 1.49 2003/11/12 18:24:59 tadejm
62 // WISHBONE slave changed and tested from only 32-bit accesss to byte access.
64 // Revision 1.48 2003/10/17 07:46:16 markom
65 // mbist signals updated according to newest convention
67 // Revision 1.47 2003/10/06 15:43:45 knguyen
68 // Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
70 // Revision 1.46 2003/01/30 13:30:22 tadejm
71 // Defer indication changed.
73 // Revision 1.45 2003/01/22 13:49:26 tadejm
74 // When control packets were received, they were ignored in some cases.
76 // Revision 1.44 2003/01/21 12:09:40 mohor
77 // When receiving normal data frame and RxFlow control was switched on, RXB
78 // interrupt was not set.
80 // Revision 1.43 2002/11/22 01:57:06 mohor
81 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
84 // Revision 1.42 2002/11/21 00:09:19 mohor
85 // TPauseRq synchronized to tx_clk.
87 // Revision 1.41 2002/11/19 18:13:49 mohor
88 // r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
90 // Revision 1.40 2002/11/19 17:34:25 mohor
91 // AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
92 // that a frame was received because of the promiscous mode.
94 // Revision 1.39 2002/11/18 17:31:55 mohor
95 // wb_rst_i is used for MIIM reset.
97 // Revision 1.38 2002/11/14 18:37:20 mohor
98 // r_Rst signal does not reset any module any more and is removed from the design.
100 // Revision 1.37 2002/11/13 22:25:36 tadejm
101 // All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
103 // Revision 1.36 2002/10/18 17:04:20 tadejm
104 // Changed BIST scan signals.
106 // Revision 1.35 2002/10/11 13:36:58 mohor
107 // Typo error fixed. (When using Bist)
109 // Revision 1.34 2002/10/10 16:49:50 mohor
110 // Signals for WISHBONE B3 compliant interface added.
112 // Revision 1.33 2002/10/10 16:29:30 mohor
115 // Revision 1.32 2002/09/20 17:12:58 mohor
116 // CsMiss added. When address between 0x800 and 0xfff is accessed within
117 // Ethernet Core, error acknowledge is generated.
119 // Revision 1.31 2002/09/12 14:50:17 mohor
120 // CarrierSenseLost bug fixed when operating in full duplex mode.
122 // Revision 1.30 2002/09/10 10:35:23 mohor
123 // Ethernet debug registers removed.
125 // Revision 1.29 2002/09/09 13:03:13 mohor
126 // Error acknowledge is generated when accessing BDs and RST bit in the
127 // MODER register (r_Rst) is set.
129 // Revision 1.28 2002/09/04 18:44:10 mohor
130 // Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
133 // Revision 1.27 2002/07/25 18:15:37 mohor
134 // RxAbort changed. Packets received with MRxErr (from PHY) are also
137 // Revision 1.26 2002/07/17 18:51:50 mohor
138 // EXTERNAL_DMA removed. External DMA not supported.
140 // Revision 1.25 2002/05/03 10:15:50 mohor
141 // Outputs registered. Reset changed for eth_wishbone module.
143 // Revision 1.24 2002/04/22 14:15:42 mohor
144 // Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
145 // selected in eth_defines.v
147 // Revision 1.23 2002/03/25 13:33:53 mohor
148 // md_padoen_o changed to md_padoe_o. Signal was always active high, just
149 // name was incorrect.
151 // Revision 1.22 2002/02/26 16:59:54 mohor
152 // Small fixes for external/internal DMA missmatches.
154 // Revision 1.21 2002/02/26 16:21:00 mohor
155 // Interrupts changed in the top file
157 // Revision 1.20 2002/02/18 10:40:17 mohor
160 // Revision 1.19 2002/02/16 14:03:44 mohor
161 // Registered trimmed. Unused registers removed.
163 // Revision 1.18 2002/02/16 13:06:33 mohor
164 // EXTERNAL_DMA used instead of WISHBONE_DMA.
166 // Revision 1.17 2002/02/16 07:15:27 mohor
167 // Testbench fixed, code simplified, unused signals removed.
169 // Revision 1.16 2002/02/15 13:49:39 mohor
170 // RxAbort is connected differently.
172 // Revision 1.15 2002/02/15 11:38:26 mohor
173 // Changes that were lost when updating from 1.11 to 1.14 fixed.
175 // Revision 1.14 2002/02/14 20:19:11 billditt
176 // Modified for Address Checking,
177 // addition of eth_addrcheck.v
179 // Revision 1.13 2002/02/12 17:03:03 mohor
180 // HASH0 and HASH1 registers added. Registers address width was
181 // changed to 8 bits.
183 // Revision 1.12 2002/02/11 09:18:22 mohor
184 // Tx status is written back to the BD.
186 // Revision 1.11 2002/02/08 16:21:54 mohor
187 // Rx status is written back to the BD.
189 // Revision 1.10 2002/02/06 14:10:21 mohor
190 // non-DMA host interface added. Select the right configutation in eth_defines.
192 // Revision 1.9 2002/01/23 10:28:16 mohor
193 // Link in the header changed.
195 // Revision 1.8 2001/12/05 15:00:16 mohor
196 // RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
197 // instead of the number of RX descriptors).
199 // Revision 1.7 2001/12/05 10:45:59 mohor
200 // ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
202 // Revision 1.6 2001/10/19 11:24:29 mohor
203 // Number of addresses (wb_adr_i) minimized.
205 // Revision 1.5 2001/10/19 08:43:51 mohor
206 // eth_timescale.v changed to timescale.v This is done because of the
207 // simulation of the few cores in a one joined project.
209 // Revision 1.4 2001/10/18 12:07:11 mohor
210 // Status signals changed, Adress decoding changed, interrupt controller
213 // Revision 1.3 2001/09/24 15:02:56 mohor
214 // Defines changed (All precede with ETH_). Small changes because some
215 // tools generate warnings when two operands are together. Synchronization
216 // between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
219 // Revision 1.2 2001/08/15 14:03:59 mohor
220 // Signal names changed on the top level for easier pad insertion (ASIC).
222 // Revision 1.1 2001/08/06 14:44:29 mohor
223 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
224 // Include files fixed to contain no path.
225 // File names and module names changed ta have a eth_ prologue in the name.
226 // File eth_timescale.v is used to define timescale
227 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
228 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
229 // and Mdo_OE. The bidirectional signal must be created on the top level. This
230 // is done due to the ASIC tools.
232 // Revision 1.2 2001/08/02 09:25:31 mohor
233 // Unconnected signals are now connected.
235 // Revision 1.1 2001/07/30 21:23:42 mohor
236 // Directory structure changed. Files checked and joind together.
243 `include "eth_defines.v"
244 `include "timescale.v"
250 wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
253 wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
256 m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
257 m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
258 m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
260 `ifdef ETH_WISHBONE_B3
261 m_wb_cti_o, m_wb_bte_o,
265 mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
268 mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
271 mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
278 // debug chain signals
279 mbist_si_i, // bist scan serial in
280 mbist_so_o, // bist scan serial out
281 mbist_ctrl_i // bist chain shift control
291 input wb_clk_i; // WISHBONE clock
292 input wb_rst_i; // WISHBONE reset
293 input [31:0] wb_dat_i; // WISHBONE data input
294 output [31:0] wb_dat_o; // WISHBONE data output
295 output wb_err_o; // WISHBONE error output
298 input [11:2] wb_adr_i; // WISHBONE address input
299 input [3:0] wb_sel_i; // WISHBONE byte select input
300 input wb_we_i; // WISHBONE write enable input
301 input wb_cyc_i; // WISHBONE cycle input
302 input wb_stb_i; // WISHBONE strobe input
303 output wb_ack_o; // WISHBONE acknowledge output
306 output [31:0] m_wb_adr_o;
307 output [3:0] m_wb_sel_o;
309 input [31:0] m_wb_dat_i;
310 output [31:0] m_wb_dat_o;
316 wire [29:0] m_wb_adr_tmp;
318 `ifdef ETH_WISHBONE_B3
319 output [2:0] m_wb_cti_o; // Cycle Type Identifier
320 output [1:0] m_wb_bte_o; // Burst Type Extension
324 input mtx_clk_pad_i; // Transmit clock (from PHY)
325 output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
326 output mtxen_pad_o; // Transmit enable (to PHY)
327 output mtxerr_pad_o; // Transmit error (to PHY)
330 input mrx_clk_pad_i; // Receive clock (from PHY)
331 input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
332 input mrxdv_pad_i; // Receive data valid (from PHY)
333 input mrxerr_pad_i; // Receive data error (from PHY)
336 input mcoll_pad_i; // Collision (from PHY)
337 input mcrs_pad_i; // Carrier sense (from PHY)
339 // MII Management interface
340 input md_pad_i; // MII data input (from I/O cell)
341 output mdc_pad_o; // MII Management data clock (to PHY)
342 output md_pad_o; // MII data output (to I/O cell)
343 output md_padoe_o; // MII data output enable (to I/O cell)
345 output int_o; // Interrupt output
349 input mbist_si_i; // bist scan serial in
350 output mbist_so_o; // bist scan serial out
351 input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
356 wire [15:0] r_CtrlData;
365 wire [15:0] Prsd; // Read Status Data (data read from the PHY)
368 wire UpdateMIIRX_DATAReg;
380 reg WillSendControlFrame_sync1;
381 reg WillSendControlFrame_sync2;
382 reg WillSendControlFrame_sync3;
391 // Connecting Miim module
394 .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
395 .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
396 .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
397 .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
398 .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
399 .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
400 .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
406 wire [3:0] RegCs; // Connected to registers
407 wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
408 wire r_RecSmall; // Receive small frames
409 wire r_LoopBck; // Loopback
410 wire r_TxEn; // Tx Enable
411 wire r_RxEn; // Rx Enable
413 wire MRxDV_Lb; // Muxed MII receive data valid
414 wire MRxErr_Lb; // Muxed MII Receive Error
415 wire [3:0] MRxD_Lb; // Muxed MII Receive Data
416 wire Transmitting; // Indication that TxEthMAC is transmitting
417 wire r_HugEn; // Huge packet enable
418 wire r_DlyCrcEn; // Delayed CRC enabled
419 wire [15:0] r_MaxFL; // Maximum frame length
421 wire [15:0] r_MinFL; // Minimum frame length
423 wire DribbleNibble; // Extra nibble received
424 wire ReceivedPacketTooBig; // Received packet is too big
425 wire [47:0] r_MAC; // MAC address
426 wire LoadRxStatus; // Rx status was loaded
427 wire [31:0] r_HASH0; // HASH table, lower 4 bytes
428 wire [31:0] r_HASH1; // HASH table, upper 4 bytes
429 wire [7:0] r_TxBDNum; // Receive buffer descriptor number
430 wire [6:0] r_IPGT; //
431 wire [6:0] r_IPGR1; //
432 wire [6:0] r_IPGR2; //
433 wire [5:0] r_CollValid; //
434 wire [15:0] r_TxPauseTV; // Transmit PAUSE value
435 wire r_TxPauseRq; // Transmit PAUSE request
437 wire [3:0] r_MaxRet; //
440 wire r_TxFlow; // Tx flow control enable
441 wire r_IFG; // Minimum interframe gap for incoming packets
443 wire TxB_IRQ; // Interrupt Tx Buffer
444 wire TxE_IRQ; // Interrupt Tx Error
445 wire RxB_IRQ; // Interrupt Rx Buffer
446 wire RxE_IRQ; // Interrupt Rx Error
447 wire Busy_IRQ; // Interrupt Busy (lack of buffers)
452 wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
453 wire [3:0] BDCs; // Buffer descriptor CS
454 wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
455 // but data is not valid.
476 wire ReceivedPauseFrm;
477 wire ControlFrmAddressOK;
478 wire RxStatusWriteLatched_sync2;
480 wire DeferIndication;
481 wire LateCollLatched;
483 wire RstDeferLatched;
484 wire CarrierSenseLost;
487 wire [31:0] temp_wb_dat_o;
490 `ifdef ETH_REGISTERED_OUTPUTS
491 reg temp_wb_ack_o_reg;
492 reg [31:0] temp_wb_dat_o_reg;
493 reg temp_wb_err_o_reg;
496 //assign DWord = &wb_sel_i;
497 assign ByteSelected = |wb_sel_i;
498 assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
499 assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
500 assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
501 assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
502 assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
503 assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
504 assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
505 assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
506 assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
507 assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
508 assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
510 `ifdef ETH_REGISTERED_OUTPUTS
511 assign wb_ack_o = temp_wb_ack_o_reg;
512 assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
513 assign wb_err_o = temp_wb_err_o_reg;
515 assign wb_ack_o = temp_wb_ack_o;
516 assign wb_dat_o[31:0] = temp_wb_dat_o;
517 assign wb_err_o = temp_wb_err_o;
520 `ifdef ETH_AVALON_BUS
521 // As Avalon has no corresponding "error" signal, I (erroneously) will
522 // send an ack to Avalon, even when accessing undefined memory. This
523 // is a grey area in Avalon vs. Wishbone specs: My understanding
524 // is that Avalon expects all memory addressable by the addr bus feeding
525 // a slave to be, at the very minimum, readable.
526 assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
528 assign temp_wb_ack_o = (|RegCs) | BDAck;
531 `ifdef ETH_REGISTERED_OUTPUTS
532 always @ (posedge wb_clk_i or posedge wb_rst_i)
536 temp_wb_ack_o_reg <=#Tp 1'b0;
537 temp_wb_dat_o_reg <=#Tp 32'h0;
538 temp_wb_err_o_reg <=#Tp 1'b0;
542 temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
543 temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
544 temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
550 // Connecting Ethernet registers
551 eth_registers ethreg1
553 .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
554 .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
555 .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
556 .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
557 .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
558 .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
559 .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
560 .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
561 .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
562 .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
564 .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
565 .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
566 .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
567 .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
568 .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
569 .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
570 .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
571 .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
572 .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
573 .r_TxBDNum(r_TxBDNum), .int_o(int_o),
574 .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
575 .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
576 .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
577 .SetPauseTimer(SetPauseTimer)
589 wire WillTransmit; // Will transmit (to RxEthMAC)
590 wire ResetCollision; // Reset Collision (for synchronizing collision)
591 wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
592 wire WillSendControlFrame;
594 wire ReceivedPacketGood;
595 wire ReceivedLengthOK;
597 wire LatchedCrcError;
598 wire RxLateCollision;
599 wire [3:0] RetryCntLatched;
602 wire MaxCollisionOccured;
605 wire [1:0] StateData;
607 // Connecting MACControl
608 eth_maccontrol maccontrol1
610 .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
611 .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
612 .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
613 .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
614 .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
615 .RxData(RxData), .RxValid(RxValid),
616 .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
617 .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
619 .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
620 .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
621 .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
622 .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
623 .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
624 .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
625 .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
626 .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
627 .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
628 .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
629 .SetPauseTimer(SetPauseTimer),
630 .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
635 wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
636 wire Collision; // Synchronized Collision
638 reg CarrierSense_Tx1;
639 reg CarrierSense_Tx2;
643 reg RxEnSync; // Synchronized Receive Enable
649 // Muxed MII receive data valid
650 assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
652 // Muxed MII Receive Error
653 assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
655 // Muxed MII Receive Data
656 assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
660 // Connecting TxEthMAC
661 eth_txethmac txethmac1
663 .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
664 .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
665 .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
666 .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
667 .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
668 .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
669 .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
670 .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
671 .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
672 .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
673 .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
674 .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
675 .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
681 wire [15:0] RxByteCnt;
683 wire RxByteCntGreat2;
684 wire RxByteCntMaxFrame;
687 wire RxStatePreamble;
689 wire [1:0] RxStateData;
694 // Connecting RxEthMAC
695 eth_rxethmac rxethmac1
697 .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
698 .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
699 .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
700 .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
701 .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
702 .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
703 .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
704 .StateSFD(RxStateSFD), .StateData(RxStateData),
705 .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
706 .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
707 .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
711 // MII Carrier Sense Synchronization
712 always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
716 CarrierSense_Tx1 <= #Tp 1'b0;
717 CarrierSense_Tx2 <= #Tp 1'b0;
721 CarrierSense_Tx1 <= #Tp mcrs_pad_i;
722 CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
726 assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
729 // MII Collision Synchronization
730 always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
734 Collision_Tx1 <= #Tp 1'b0;
735 Collision_Tx2 <= #Tp 1'b0;
739 Collision_Tx1 <= #Tp mcoll_pad_i;
741 Collision_Tx2 <= #Tp 1'b0;
744 Collision_Tx2 <= #Tp 1'b1;
749 // Synchronized Collision
750 assign Collision = ~r_FullD & Collision_Tx2;
754 // Delayed WillTransmit
755 always @ (posedge mrx_clk_pad_i)
757 WillTransmit_q <= #Tp WillTransmit;
758 WillTransmit_q2 <= #Tp WillTransmit_q;
762 assign Transmitting = ~r_FullD & WillTransmit_q2;
766 // Synchronized Receive Enable
767 always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
770 RxEnSync <= #Tp 1'b0;
773 RxEnSync <= #Tp r_RxEn;
778 // Synchronizing WillSendControlFrame to WB_CLK;
779 always @ (posedge wb_clk_i or posedge wb_rst_i)
782 WillSendControlFrame_sync1 <= 1'b0;
784 WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
787 always @ (posedge wb_clk_i or posedge wb_rst_i)
790 WillSendControlFrame_sync2 <= 1'b0;
792 WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
795 always @ (posedge wb_clk_i or posedge wb_rst_i)
798 WillSendControlFrame_sync3 <= 1'b0;
800 WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
803 always @ (posedge wb_clk_i or posedge wb_rst_i)
806 RstTxPauseRq <= 1'b0;
808 RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
814 // TX Pause request Synchronization
815 always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
819 TxPauseRq_sync1 <= #Tp 1'b0;
820 TxPauseRq_sync2 <= #Tp 1'b0;
821 TxPauseRq_sync3 <= #Tp 1'b0;
825 TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
826 TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
827 TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
832 always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
835 TPauseRq <= #Tp 1'b0;
837 TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
845 reg RxAbortRst_sync1;
848 // Synchronizing RxAbort to the WISHBONE clock
849 always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
852 RxAbort_latch <= #Tp 1'b0;
853 else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
854 RxAbort_latch <= #Tp 1'b1;
856 RxAbort_latch <= #Tp 1'b0;
859 always @ (posedge wb_clk_i or posedge wb_rst_i)
863 RxAbort_sync1 <= #Tp 1'b0;
864 RxAbort_wb <= #Tp 1'b0;
865 RxAbort_wb <= #Tp 1'b0;
869 RxAbort_sync1 <= #Tp RxAbort_latch;
870 RxAbort_wb <= #Tp RxAbort_sync1;
874 always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
878 RxAbortRst_sync1 <= #Tp 1'b0;
879 RxAbortRst <= #Tp 1'b0;
883 RxAbortRst_sync1 <= #Tp RxAbort_wb;
884 RxAbortRst <= #Tp RxAbortRst_sync1;
890 // Connecting Wishbone module
891 eth_wishbone wishbone
893 .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
894 .WB_DAT_O(BD_WB_DAT_O),
897 .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
898 .BDCs(BDCs), .WB_ACK_O(BDAck),
903 .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
904 .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
905 .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
907 `ifdef ETH_WISHBONE_B3
908 .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
913 .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
914 .TxUsedData(TxUsedData), .TxData(TxData),
915 .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
917 .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
920 .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
921 .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
924 .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
925 .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
926 .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
927 .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
929 .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
931 .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
932 .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
933 .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
934 .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
935 .RstDeferLatched(RstDeferLatched),
936 .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
937 .ReceivedPauseFrm(ReceivedPauseFrm)
941 .mbist_si_i (mbist_si_i),
942 .mbist_so_o (mbist_so_o),
943 .mbist_ctrl_i (mbist_ctrl_i)
947 assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
949 // Connecting MacStatus module
950 eth_macstatus macstatus1
952 .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
953 .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
954 .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
955 .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
956 .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
957 .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
958 .InvalidSymbol(InvalidSymbol),
959 .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
960 .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
961 .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
962 .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
963 .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
964 .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
965 .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
966 .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
967 .RstDeferLatched(RstDeferLatched),
968 .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
969 .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
970 .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)