1 module wb_fifo (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
2 wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);
7 output [15:0] wb_dat_o;
16 input [7:0] fifo_data_i;
17 output [7:0] fifo_data_o;
23 always @(posedge clk_i or negedge nrst_i)
28 if (wb_stb_i && wb_we_i)
32 assign fifo_we_o = 1'b1;
33 assign fifo_data_o = data_reg;
35 assign wb_ack_o = wb_stb_i;
36 assign wb_err_o = 1'b0;
37 assign wb_int_o = 1'b0;
38 assign wb_dat_o = data_reg;