1 module disp_dec(disp_dec_in, disp_dec_out);
2 input [3:0] disp_dec_in;
3 output reg [6:0] disp_dec_out;
8 4'b0000: disp_dec_out <= 7'b1000000;
9 4'b0001: disp_dec_out <= 7'b1111001;
10 4'b0010: disp_dec_out <= 7'b0100100;
11 4'b0011: disp_dec_out <= 7'b0110000;
13 4'b0100: disp_dec_out <= 7'b0011001;
14 4'b0101: disp_dec_out <= 7'b0010010;
15 4'b0110: disp_dec_out <= 7'b0000010;
16 4'b0111: disp_dec_out <= 7'b1111000;
18 4'b1000: disp_dec_out <= 7'b0000000;
19 4'b1001: disp_dec_out <= 7'b0010000;
20 4'b1010: disp_dec_out <= 7'b0001000;
21 4'b1011: disp_dec_out <= 7'b0000011;
23 4'b1100: disp_dec_out <= 7'b1000110;
24 4'b1101: disp_dec_out <= 7'b0100001;
25 4'b1110: disp_dec_out <= 7'b0000110;
26 4'b1111: disp_dec_out <= 7'b0001110;