3 use ieee.std_logic_1164.all;
4 use ieee.std_logic_unsigned.all;
8 divider : std_logic_vector(31 downto 0) := X"01F78A40"
13 nrst_i : in std_logic;
14 led2_o : out std_logic;
15 led3_o : out std_logic;
16 led4_o : out std_logic;
17 led5_o : out std_logic
22 architecture rtl of heartbeat is
25 process(clk_i, nrst_i)
26 variable counter : std_logic_vector(31 downto 0);
27 variable state : std_logic := '0';
30 if (clk_i'event AND clk_i = '1') then
32 counter := (others => '0');
38 counter := counter + 1;
39 if counter = divider then
41 counter := (others => '0');