1 //////////////////////////////////////////////////////////////////////
3 //// eth_shiftreg.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
11 //// All additional information is avaliable in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2001 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
41 // CVS Revision History
43 // $Log: eth_shiftreg.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
47 // Revision 1.6 2005/03/08 14:45:09 igorm
48 // Case statement improved for synthesys.
50 // Revision 1.5 2002/08/14 18:16:59 mohor
51 // LinkFail signal was not latching appropriate bit.
53 // Revision 1.4 2002/03/02 21:06:01 mohor
54 // LinkFail signal was not latching appropriate bit.
56 // Revision 1.3 2002/01/23 10:28:16 mohor
57 // Link in the header changed.
59 // Revision 1.2 2001/10/19 08:43:51 mohor
60 // eth_timescale.v changed to timescale.v This is done because of the
61 // simulation of the few cores in a one joined project.
63 // Revision 1.1 2001/08/06 14:44:29 mohor
64 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
65 // Include files fixed to contain no path.
66 // File names and module names changed ta have a eth_ prologue in the name.
67 // File eth_timescale.v is used to define timescale
68 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
69 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
70 // and Mdo_OE. The bidirectional signal must be created on the top level. This
71 // is done due to the ASIC tools.
73 // Revision 1.1 2001/07/30 21:23:42 mohor
74 // Directory structure changed. Files checked and joind together.
76 // Revision 1.3 2001/06/01 22:28:56 mohor
77 // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
81 `include "timescale.v"
84 module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
85 LatchByte, ShiftedBit, Prsd, LinkFail);
90 input Clk; // Input clock (Host clock)
91 input Reset; // Reset signal
92 input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
93 input Mdi; // MII input data
94 input [4:0] Fiad; // PHY address
95 input [4:0] Rgad; // Register address (within the selected PHY)
96 input [15:0]CtrlData; // Control data (data to be written to the PHY)
97 input WriteOp; // The current operation is a PHY register write operation
98 input [3:0] ByteSelect; // Byte select
99 input [1:0] LatchByte; // Byte select for latching (read operation)
101 output ShiftedBit; // Bit shifted out of the shift register
102 output[15:0]Prsd; // Read Status Data (data read from the PHY)
103 output LinkFail; // Link Integrity Signal
105 reg [7:0] ShiftReg; // Shift register for shifting the data in and out
112 // ShiftReg[7:0] :: Shift Register Data
113 always @ (posedge Clk or posedge Reset)
117 ShiftReg[7:0] <= #Tp 8'h0;
118 Prsd[15:0] <= #Tp 16'h0;
119 LinkFail <= #Tp 1'b0;
127 case (ByteSelect[3:0]) // synopsys parallel_case full_case
128 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
129 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
130 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
131 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
136 ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
139 Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
141 LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
146 Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
154 assign ShiftedBit = ShiftReg[7];