7 use ieee.std_logic_1164.all;
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic; -- PCI reset is asynchron (low active)
15 TAST_SETn :in std_logic;
16 TAST_RESn :in std_logic;
17 INT_IN_0 :in std_logic;
18 INT_IN_1 :in std_logic;
19 INT_IN_2 :in std_logic;
20 INT_IN_3 :in std_logic;
21 INT_IN_4 :in std_logic;
22 INT_IN_5 :in std_logic;
23 INT_IN_6 :in std_logic;
24 INT_IN_7 :in std_logic;
25 TRDYn :in std_logic; -- event 1 after read of Interrupt status register (low active)
26 READ_XX5_4 :in std_logic; -- event 2 after read of Interrupt status register
27 INT_RES :in std_logic_vector(7 downto 0); -- clear selected interrupts
28 INT_MASKE :in std_logic_vector(7 downto 0); -- interrupt mask register
29 INT_REG :out std_logic_vector(7 downto 0); -- interrupt status register
30 INTAn :out std_logic; -- second interrupt line for PCI analyzer
31 PCI_INTAn :out std_logic -- PCI interrupt line
36 architecture INTERRUPT_DESIGN of INTERRUPT is
38 signal SIG_TAST_Q :std_logic;
39 signal SIG_TAST_Qn :std_logic;
42 signal SIG_INTA :std_logic;
44 signal FF_A :std_logic_vector(7 downto 0);
45 signal FF_B :std_logic_vector(7 downto 0);
46 signal SET :std_logic_vector(7 downto 0);
48 signal SIG_PROPAGATE_INT :std_logic;
49 signal SIG_PROPAGATE_INT_SECOND :std_logic;
50 signal REG :std_logic_vector(7 downto 0);
57 ------------------------------------------------------
60 if (PCI_CLOCK'event and PCI_CLOCK ='1') then
62 -- THIS IS BROKEN (it cycles the interrupt)
63 SIG_TAST_Q <= not (TAST_SETn and SIG_TAST_Qn);
64 SIG_TAST_Qn <= not (TAST_RESn and SIG_TAST_Q);
69 ------------------------------------------------------
73 if (PCI_RSTn = '0') then
78 elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
85 FF_A(0) <= INT_IN_0 ; -- Receive FIFO Empty Flag
87 FF_A(1) <= INT_IN_1 ; -- Send FIFO Half Full
99 SET <= FF_A AND not FF_B;
104 process (PCI_CLOCK,PCI_RSTn)
106 if (PCI_RSTn = '0') then
109 elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
113 elsif(SIG_TAST_Q = '1') then
114 REG <= "00000000" or SET;
116 elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
117 REG <= (REG AND NOT INT_RES) OR SET;
125 (REG(0) AND INT_MASKE(0))
126 OR (REG(1) AND INT_MASKE(1))
127 OR (REG(2) AND INT_MASKE(2))
128 OR (REG(3) AND INT_MASKE(3))
129 OR (REG(4) AND INT_MASKE(4))
130 OR (REG(5) AND INT_MASKE(5))
131 OR (REG(6) AND INT_MASKE(6))
132 OR (REG(7) AND INT_MASKE(7));
136 if(PCI_CLOCK'event and PCI_CLOCK = '1') then
137 SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
142 INTAn <= not SIG_PROPAGATE_INT_SECOND;
143 PCI_INTAn <= '0' when SIG_PROPAGATE_INT_SECOND = '0' else 'Z';
147 end architecture INTERRUPT_DESIGN;