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[fpga-games] / galaxian / src / altera / alt_ram_256_8.v

// megafunction wizard: %RAM: 1-PORT%\r
// GENERATION: STANDARD\r
// VERSION: WM1.0\r
// MODULE: altsyncram \r
\r
// ============================================================\r
// File Name: alt_ram_256_8.v\r
// Megafunction Name(s):\r
// 			altsyncram\r
// ============================================================\r
// ************************************************************\r
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
// ************************************************************\r
\r
\r
//Copyright (C) 1991-2003 Altera Corporation\r
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),\r
//support information,  device programming or simulation file,  and any other\r
//associated  documentation or information  provided by  Altera  or a partner\r
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only\r
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any\r
//other  use  of such  megafunction  design,  netlist,  support  information,\r
//device programming or simulation file,  or any other  related documentation\r
//or information  is prohibited  for  any  other purpose,  including, but not\r
//limited to  modification,  reverse engineering,  de-compiling, or use  with\r
//any other  silicon devices,  unless such use is  explicitly  licensed under\r
//a separate agreement with  Altera  or a megafunction partner.  Title to the\r
//intellectual property,  including patents,  copyrights,  trademarks,  trade\r
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,\r
//support  information,  device programming or simulation file,  or any other\r
//related documentation or information provided by  Altera  or a megafunction\r
//partner, remains with Altera, the megafunction partner, or their respective\r
//licensors. No other licenses, including any licenses needed under any third\r
//party's intellectual property, are provided herein.\r
\r
\r
module alt_ram_256_8 (\r
	address,\r
	clock,\r
	data,\r
	wren,\r
	q);\r
\r
	input	[7:0]  address;\r
	input	  clock;\r
	input	[7:0]  data;\r
	input	  wren;\r
	output	[7:0]  q;\r
\r
	wire [7:0] sub_wire0;\r
	wire [7:0] q = sub_wire0[7:0];\r
\r
	altsyncram	altsyncram_component (\r
				.wren_a (wren),\r
				.clock0 (clock),\r
				.address_a (address),\r
				.data_a (data),\r
				.q_a (sub_wire0));\r
	defparam\r
		altsyncram_component.intended_device_family = "Cyclone",\r
		altsyncram_component.width_a = 8,\r
		altsyncram_component.widthad_a = 8,\r
		altsyncram_component.numwords_a = 256,\r
		altsyncram_component.operation_mode = "SINGLE_PORT",\r
		altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
		altsyncram_component.indata_aclr_a = "NONE",\r
		altsyncram_component.wrcontrol_aclr_a = "NONE",\r
		altsyncram_component.address_aclr_a = "NONE",\r
		altsyncram_component.outdata_aclr_a = "NONE",\r
		altsyncram_component.width_byteena_a = 1,\r
		altsyncram_component.ram_block_type = "AUTO",\r
		altsyncram_component.lpm_type = "altsyncram";\r
\r
\r
endmodule\r
\r
// ============================================================\r
// CNX file retrieval info\r
// ============================================================\r
// Retrieval info: PRIVATE: WidthData NUMERIC "8"\r
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"\r
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"\r
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"\r
// Retrieval info: PRIVATE: RegData NUMERIC "1"\r
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"\r
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
// Retrieval info: PRIVATE: AclrData NUMERIC "0"\r
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"\r
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
// Retrieval info: PRIVATE: MIFfilename STRING ""\r
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"\r
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"\r
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"\r
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"\r
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]\r
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]\r
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]\r
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren\r
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0\r
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\r
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\r
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\r
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r