cleanup clocks
[fpga-games] / galaxian / src / mc_adec.v
CommitLineData
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1//---------------------------------------------------------------------\r
2// FPGA GALAXIAN ADDRESS DECDER\r
3//\r
4// Version : 2.01\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP. \r
17//---------------------------------------------------------------------\r
18//\r
19//GALAXIAN Address Map\r
20//\r
21// Address Item(R..read-mode W..wight-mode) Parts \r
22//0000 - 1FFF CPU-ROM..R ( 7H or 7K ) \r
23//2000 - 3FFF CPU-ROM..R ( 7L )\r
24//4000 - 47FF CPU-RAM..RW ( 7N & 7P ) \r
25//5000 - 57FF VID-RAM..RW \r
26//5800 - 5FFF OBJ-RAM..RW\r
27//6000 - SW0..R LAMP......W\r
28//6800 - SW1..R SOUND.....W\r
29//7000 - DIP..R \r
30//7001 NMI_ON....W\r
31//7004 STARS_ON..W\r
32//7006 H_FLIP....W\r
33//7007 V-FLIP....W\r
34//7800 WDR..R PITCH.....W\r
35//\r
36//W MODE\r
37//6000 - 6002 \r
38//6003 COIN CNTR \r
39//6004 - 6007 SOUND CONTROL(OSC)\r
40//\r
41//6800 SOUND CONTROL(FS1)\r
42//6801 SOUND CONTROL(FS2)\r
43//6802 SOUND CONTROL(FS3)\r
44//6803 SOUND CONTROL(HIT)\r
45//6805 SOUND CONTROL(SHOT)\r
46//6806 SOUND CONTROL(VOL1)\r
47//6807 SOUND CONTROL(VOL2)\r
48//\r
49\r
50module mc_adec(\r
51\r
52I_CLK_12M,\r
53I_CLK_6M,\r
54I_CPU_CLK,\r
55I_RSTn,\r
56\r
57I_CPU_A,\r
58I_CPU_D,\r
59I_MREQn,\r
60I_RFSHn,\r
61I_RDn,\r
62I_WRn,\r
63I_H_BL,\r
64I_V_BLn,\r
65\r
66O_WAITn,\r
67O_NMIn,\r
68O_CPU_ROM_CSn,\r
69O_CPU_RAM_RDn,\r
70O_CPU_RAM_WRn,\r
71O_CPU_RAM_CSn,\r
72O_OBJ_RAM_RDn,\r
73O_OBJ_RAM_WRn,\r
74O_OBJ_RAM_RQn,\r
75O_VID_RAM_RDn,\r
76O_VID_RAM_WRn,\r
77O_SW0_OEn,\r
78O_SW1_OEn,\r
79O_DIP_OEn,\r
80O_WDR_OEn,\r
81O_LAMP_WEn,\r
82O_SOUND_WEn,\r
83O_PITCHn,\r
84O_H_FLIP,\r
85O_V_FLIP,\r
86O_BD_G,\r
87O_STARS_ON\r
88\r
89);\r
90\r
91\r
92input I_CLK_12M;\r
93input I_CLK_6M;\r
94input I_CPU_CLK;\r
95input I_RSTn;\r
96\r
97input [15:0]I_CPU_A;\r
98input I_CPU_D;\r
99input I_MREQn;\r
100input I_RFSHn;\r
101input I_RDn;\r
102input I_WRn;\r
103input I_H_BL;\r
104input I_V_BLn;\r
105\r
106output O_WAITn;\r
107output O_NMIn;\r
108output O_CPU_ROM_CSn;\r
109output O_CPU_RAM_RDn;\r
110output O_CPU_RAM_WRn;\r
111output O_CPU_RAM_CSn;\r
112output O_OBJ_RAM_RDn;\r
113output O_OBJ_RAM_WRn;\r
114output O_OBJ_RAM_RQn;\r
115output O_VID_RAM_RDn;\r
116output O_VID_RAM_WRn;\r
117output O_SW0_OEn;\r
118output O_SW1_OEn;\r
119output O_DIP_OEn;\r
120output O_WDR_OEn;\r
121output O_LAMP_WEn;\r
122output O_SOUND_WEn;\r
123output O_PITCHn;\r
124output O_H_FLIP;\r
125output O_V_FLIP;\r
126output O_BD_G;\r
127output O_STARS_ON;\r
128\r
129\r
130wire [3:0]W_8E1_Q;\r
131wire [3:0]W_8E2_Q;\r
132wire [7:0]W_8P_Q,W_8N_Q,W_8M_Q;\r
133reg [7:0]W_9N_Q;\r
134wire W_NMI_ONn = W_9N_Q[1]; // galaxian\r
135//------ CPU WAITn ---------------------------------------------- \r
136\r
137reg W_6S1_Q,W_6S1_Qn;\r
138reg W_6S2_Qn;\r
139\r
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140assign O_WAITn = W_6S1_Qn;\r
141//assign O_WAITn = 1'b1 ; // No Wait\r
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142\r
143always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
144begin\r
145 if(I_V_BLn == 1'b0)begin\r
146 W_6S1_Q <= 1'b0;\r
147 W_6S1_Qn <= 1'b1;\r
148 end\r
149 else begin\r
150 W_6S1_Q <= ~(I_H_BL | W_8P_Q[2]);\r
151 W_6S1_Qn <= I_H_BL | W_8P_Q[2];\r
152 end\r
153end\r
154\r
155always@(negedge I_CPU_CLK)\r
156begin\r
157 W_6S2_Qn <= ~W_6S1_Q;\r
158end\r
159//------ CPU NMIn ----------------------------------------------- \r
160wire W_V_BL = ~I_V_BLn;\r
161reg O_NMIn;\r
162always@(posedge W_V_BL or negedge W_NMI_ONn)\r
163begin\r
164 if(~W_NMI_ONn)\r
165 O_NMIn <= 1'b1;\r
166 else\r
167 O_NMIn <= 1'b0;\r
168end\r
169//----------------------------------------------------------------- \r
170logic_74xx139 U_8E1(\r
171\r
172.I_G(I_MREQn),\r
173.I_Sel(I_CPU_A[15:14]),\r
174.O_Q(W_8E1_Q)\r
175\r
176);\r
177\r
178//-------- CPU_ROM CS 0000 - 3FFF --------------------------- \r
179logic_74xx139 U_8E2(\r
180\r
181.I_G(I_RDn),\r
182.I_Sel({W_8E1_Q[0],I_CPU_A[13]}),\r
183.O_Q(W_8E2_Q)\r
184\r
185);\r
186\r
187assign O_CPU_ROM_CSn = W_8E2_Q[0]&W_8E2_Q[1] ; // 0000 - 3FFF\r
188//-----------------------------------------------------------------\r
189// ADDRESS\r
190// W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE \r
191// W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1\r
192// W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE \r
193// W_8E1_Q[3] = C000 - FFFF\r
194\r
195logic_74xx138 U_8P(\r
196\r
197.I_G1(I_RFSHn),\r
198.I_G2a(W_8E1_Q[1]), // <= *1\r
199.I_G2b(W_8E1_Q[1]), // <= *1\r
200.I_Sel(I_CPU_A[13:11]),\r
201.O_Q(W_8P_Q)\r
202\r
203);\r
204\r
205logic_74xx138 U_8N(\r
206\r
207.I_G1(1'b1),\r
208.I_G2a(I_RDn),\r
209.I_G2b(W_8E1_Q[1]), // <= *1\r
210.I_Sel(I_CPU_A[13:11]),\r
211.O_Q(W_8N_Q)\r
212\r
213);\r
214\r
215logic_74xx138 U_8M(\r
216\r
217//.I_G1(W_6S2_Qn),\r
218.I_G1(1'b1), // No Wait\r
219.I_G2a(I_WRn),\r
220.I_G2b(W_8E1_Q[1]), // <= *1\r
221.I_Sel(I_CPU_A[13:11]),\r
222.O_Q(W_8M_Q)\r
223\r
224);\r
225\r
226assign O_BD_G = ~(W_8E1_Q[0]&W_8P_Q[0]); //\r
227assign O_OBJ_RAM_RQn = W_8P_Q[3]; //\r
228\r
229assign O_CPU_RAM_CSn = W_8N_Q[0]&W_8M_Q[0]; //\r
230assign O_CPU_RAM_RDn = W_8N_Q[0]; //\r
231assign O_CPU_RAM_WRn = W_8M_Q[0]; //\r
232assign O_VID_RAM_RDn = W_8N_Q[2]; //\r
233assign O_OBJ_RAM_RDn = W_8N_Q[3]; //\r
234assign O_SW0_OEn = W_8N_Q[4]; // \r
235assign O_SW1_OEn = W_8N_Q[5]; // \r
236assign O_DIP_OEn = W_8N_Q[6]; // \r
237assign O_WDR_OEn = W_8N_Q[7]; // \r
238\r
239assign O_VID_RAM_WRn = W_8M_Q[2]; // \r
240assign O_OBJ_RAM_WRn = W_8M_Q[3]; // \r
241assign O_LAMP_WEn = W_8M_Q[4]; // \r
242assign O_SOUND_WEn = W_8M_Q[5]; // \r
243\r
244assign O_PITCHn = W_8M_Q[7]; // \r
245\r
246//--- Parts 9N ---------\r
247\r
248always@(posedge I_CLK_12M or negedge I_RSTn)\r
249begin\r
250 if(I_RSTn == 1'b0)begin\r
251 W_9N_Q <= 0;\r
252 end \r
253 else begin\r
254 if(W_8M_Q[6] == 1'b0)begin\r
255 case(I_CPU_A[2:0])\r
256 3'h0 : W_9N_Q[0] <= I_CPU_D;\r
257 3'h1 : W_9N_Q[1] <= I_CPU_D;\r
258 3'h2 : W_9N_Q[2] <= I_CPU_D;\r
259 3'h3 : W_9N_Q[3] <= I_CPU_D;\r
260 3'h4 : W_9N_Q[4] <= I_CPU_D;\r
261 3'h5 : W_9N_Q[5] <= I_CPU_D;\r
262 3'h6 : W_9N_Q[6] <= I_CPU_D;\r
263 3'h7 : W_9N_Q[7] <= I_CPU_D;\r
264 endcase\r
265 end\r
266 end\r
267end\r
268\r
269assign O_STARS_ON = W_9N_Q[4]; // \r
270assign O_H_FLIP = W_9N_Q[6]; // \r
271assign O_V_FLIP = W_9N_Q[7]; // \r
272\r
273\r
36a47d3c 274endmodule\r
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