cleanup clocks
[fpga-games] / galaxian / src / mc_hv_count.v
CommitLineData
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1//---------------------------------------------------------------------\r
2// FPGA MOONCRESTA H & V COUNTER \r
3//\r
4// Version : 2.00\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 9-22 \r
15//---------------------------------------------------------------------\r
16// MoonCrest hv_count\r
17// H_CNT 0 - 255 , 384 - 511 Total 384 count\r
18// V_CNT 0 - 255 , 504 - 511 Total 264 count\r
19//-----------------------------------------------------------------------------------------\r
20// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
21// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
22//-----------------------------------------------------------------------------------------\r
23// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
24// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
25//-----------------------------------------------------------------------------------------\r
26\r
27module mc_hv_count(\r
28\r
29I_CLK, // 6MHz\r
30I_RSTn,\r
31\r
32O_H_CNT,\r
33O_H_SYNC,\r
34O_H_BL,\r
35O_V_CNT,\r
36O_V_SYNC,\r
37O_V_BLn,\r
38O_V_BL2n,\r
39O_C_BLn\r
40\r
41);\r
42\r
43input I_CLK,I_RSTn;\r
44output [8:0]O_H_CNT;\r
45output O_H_SYNC;\r
46output O_H_BL;\r
47output O_V_BL2n;\r
48output [7:0]O_V_CNT;\r
49output O_V_SYNC;\r
50output O_V_BLn;\r
51\r
52output O_C_BLn;\r
53\r
54//------- H_COUNT ---------------------------------------- \r
55reg [8:0]H_CNT;\r
56always@(posedge I_CLK)\r
57begin\r
58 H_CNT <= H_CNT==255 ? 384 : H_CNT +1 ;\r
59end\r
60assign O_H_CNT = H_CNT[8:0];\r
61\r
62//------- H_SYNC ----------------------------------------\r
63\r
c3bcc38a 64reg H_SYNC;\r
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65always@(posedge H_CNT[4] or negedge H_CNT[8]) \r
66begin\r
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67 if(H_CNT[8]==1'b0) H_SYNC <= 1'b0;\r
68 else H_SYNC <= (~H_CNT[6]& H_CNT[5]);\r
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69end\r
70\r
71assign O_H_SYNC = H_SYNC;\r
72//------- H_BL ------------------------------------------\r
73\r
74reg H_BL;\r
75\r
76always@(posedge I_CLK)\r
77begin\r
78 case(H_CNT[8:0])\r
79 387:H_BL<=1'b1;\r
80 503:H_BL<=1'b0;\r
81 default:;\r
82 endcase\r
83end\r
84\r
85assign O_H_BL = H_BL;\r
86//------- V_COUNT ---------------------------------------- \r
87reg [8:0]V_CNT;\r
88always@(posedge H_SYNC or negedge I_RSTn)\r
89begin\r
90 if(I_RSTn==1'b0)\r
91 V_CNT <= 0;\r
92 else\r
93 V_CNT <= V_CNT==255 ? 504 : V_CNT +1 ;\r
94end\r
95assign O_V_CNT = V_CNT[7:0];\r
96assign O_V_SYNC = V_CNT[8];\r
97\r
98//------- V_BLn ------------------------------------------\r
99\r
100reg V_BLn;\r
101always@(posedge H_SYNC)\r
102begin\r
103 case(V_CNT[7:0])\r
104 239: V_BLn <= 0;\r
105 15: V_BLn <= 1;\r
106 default:;\r
107 endcase\r
108end\r
109\r
110reg V_BL2n;\r
111always@(posedge H_SYNC)\r
112begin\r
113 case(V_CNT[7:0])\r
114 239: V_BL2n <= 0;\r
115 16: V_BL2n <= 1;\r
116 default:;\r
117 endcase\r
118end\r
119\r
120assign O_V_BLn = V_BLn;\r
121assign O_V_BL2n = V_BL2n;\r
122//------- C_BLn ------------------------------------------\r
123\r
124assign O_C_BLn = ~(~V_BLn | H_CNT[8]);\r
125\r
c3bcc38a 126endmodule\r
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