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782690d0 MG |
1 | -- |
2 | -- T80 Registers, technology independent | |
3 | -- | |
4 | -- Version : 0244 | |
5 | -- | |
6 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) | |
7 | -- | |
8 | -- All rights reserved | |
9 | -- | |
10 | -- Redistribution and use in source and synthezised forms, with or without | |
11 | -- modification, are permitted provided that the following conditions are met: | |
12 | -- | |
13 | -- Redistributions of source code must retain the above copyright notice, | |
14 | -- this list of conditions and the following disclaimer. | |
15 | -- | |
16 | -- Redistributions in synthesized form must reproduce the above copyright | |
17 | -- notice, this list of conditions and the following disclaimer in the | |
18 | -- documentation and/or other materials provided with the distribution. | |
19 | -- | |
20 | -- Neither the name of the author nor the names of other contributors may | |
21 | -- be used to endorse or promote products derived from this software without | |
22 | -- specific prior written permission. | |
23 | -- | |
24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE | |
28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | -- POSSIBILITY OF SUCH DAMAGE. | |
35 | -- | |
36 | -- Please report bugs to the author, but before you do so, please | |
37 | -- make sure that this is not a derivative work and that | |
38 | -- you have the latest version of this file. | |
39 | -- | |
40 | -- The latest version of this file can be found at: | |
41 | -- http://www.opencores.org/cvsweb.shtml/t51/ | |
42 | -- | |
43 | -- Limitations : | |
44 | -- | |
45 | -- File history : | |
46 | -- | |
47 | -- 0242 : Initial release | |
48 | -- | |
49 | -- 0244 : Changed to single register file | |
50 | -- | |
51 | ||
52 | library IEEE; | |
53 | use IEEE.std_logic_1164.all; | |
54 | use IEEE.numeric_std.all; | |
55 | ||
56 | entity T80_Reg is | |
57 | port( | |
58 | Clk : in std_logic; | |
59 | CEN : in std_logic; | |
60 | WEH : in std_logic; | |
61 | WEL : in std_logic; | |
62 | AddrA : in std_logic_vector(2 downto 0); | |
63 | AddrB : in std_logic_vector(2 downto 0); | |
64 | AddrC : in std_logic_vector(2 downto 0); | |
65 | DIH : in std_logic_vector(7 downto 0); | |
66 | DIL : in std_logic_vector(7 downto 0); | |
67 | DOAH : out std_logic_vector(7 downto 0); | |
68 | DOAL : out std_logic_vector(7 downto 0); | |
69 | DOBH : out std_logic_vector(7 downto 0); | |
70 | DOBL : out std_logic_vector(7 downto 0); | |
71 | DOCH : out std_logic_vector(7 downto 0); | |
72 | DOCL : out std_logic_vector(7 downto 0) | |
73 | ); | |
74 | end T80_Reg; | |
75 | ||
76 | architecture rtl of T80_Reg is | |
77 | ||
78 | type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); | |
79 | signal RegsH : Register_Image(0 to 7); | |
80 | signal RegsL : Register_Image(0 to 7); | |
81 | ||
82 | begin | |
83 | ||
84 | process (Clk) | |
85 | begin | |
86 | if Clk'event and Clk = '1' then | |
87 | if CEN = '1' then | |
88 | if WEH = '1' then | |
89 | RegsH(to_integer(unsigned(AddrA))) <= DIH; | |
90 | end if; | |
91 | if WEL = '1' then | |
92 | RegsL(to_integer(unsigned(AddrA))) <= DIL; | |
93 | end if; | |
94 | end if; | |
95 | end if; | |
96 | end process; | |
97 | ||
98 | DOAH <= RegsH(to_integer(unsigned(AddrA))); | |
99 | DOAL <= RegsL(to_integer(unsigned(AddrA))); | |
100 | DOBH <= RegsH(to_integer(unsigned(AddrB))); | |
101 | DOBL <= RegsL(to_integer(unsigned(AddrB))); | |
102 | DOCH <= RegsH(to_integer(unsigned(AddrC))); | |
103 | DOCL <= RegsL(to_integer(unsigned(AddrC))); | |
104 | ||
105 | end; |