git.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_clock.v

   1 //---------------------------------------------------------------------
   2 // FPGA MOONCRESTA   CLOCK GEN
   3 //
   4 // Version : 1.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 //---------------------------------------------------------------------
  15
  16
  17
  18 module mc_clock(
  19
  20 I_CLK_36M,
  21 O_CLK_18M,
  22 O_CLK_12M,
  23 O_CLK_06M,
  24 O_CLK_06Mn
  25
  26 );
  27
  28 input I_CLK_36M;
  29 output O_CLK_18M;
  30 output O_CLK_12M;
  31 output O_CLK_06M;
  32 output O_CLK_06Mn;
  33
  34 // 2/3 clock divider(duty 33%)
  35 //I_CLK   1010101010101010101
  36 //c_ff10  0011110011110011110
  37 //c_ff11  0011000011000011000
  38 //c_ff20  0000110000110000110
  39 //c_ff21  0110000110000110000
  40 //O_12M   0000110110110110110
  41 reg [1:0] state;
  42 reg clk_12m;
  43 initial state = 0;
  44 initial clk_12m = 0;
  45
  46 // 2/3 clock         (duty 66%)
  47 always @(posedge I_CLK_36M)
  48 begin
  49    case (state)
  50       2'd0: state <= 2'd1;
  51       2'd1: state <= 2'd2;
  52       2'd2: state <= 2'd0;
  53       2'd3: state <= 2'd0;
  54    endcase
  55
  56    if (state == 2'd2)
  57       clk_12m = 0;
  58    else
  59       clk_12m = 1;
  60 end
  61
  62 assign O_CLK_12M = clk_12m;
  63
  64 reg CLK_18M;
  65 always @(posedge I_CLK_36M)
  66 begin
  67    CLK_18M <= ~ CLK_18M;
  68 end
  69 assign O_CLK_18M = CLK_18M;
  70
  71 // 1/3 clock divider (duty 50%)
  72 reg CLK_6M;
  73 reg CLK_6Mn;
  74
  75 always @(posedge O_CLK_12M)
  76 begin
  77    CLK_6M  <= ~CLK_6M;
  78    CLK_6Mn <= CLK_6M;
  79 end
  80
  81 assign O_CLK_06M = CLK_6M;
  82 assign O_CLK_06Mn = CLK_6Mn;
  83
  84 endmodule