64541bcaca24aa1c5a006d4b1e19d73c037af158
[fpga-games] / galaxian / src / dcm.v
1 // Module mc_dcm
2 // Generated by Xilinx Architecture Wizard
3 // Written for synthesis tool: XST
4 // Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
5 // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
6 `timescale 1ns / 1ps
7
8 module mc_dcm(CLKIN_IN,
9 RST_IN,
10 CLKFX_OUT,
11 CLKIN_IBUFG_OUT,
12 CLK0_OUT,
13 LOCKED_OUT);
14
15 input CLKIN_IN;
16 input RST_IN;
17 output CLKFX_OUT;
18 output CLKIN_IBUFG_OUT;
19 output CLK0_OUT;
20 output LOCKED_OUT;
21
22 wire CLKFB_IN;
23 wire CLKFX_BUF;
24 wire CLKIN_IBUFG;
25 wire CLK0_BUF;
26 wire GND_BIT;
27
28 assign GND_BIT = 0;
29 assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
30 assign CLK0_OUT = CLKFB_IN;
31 BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
32 .O(CLKFX_OUT));
33 IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
34 .O(CLKIN_IBUFG));
35 BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
36 .O(CLKFB_IN));
37 DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
38 .CLKIN(CLKIN_IBUFG),
39 .DSSEN(GND_BIT),
40 .PSCLK(GND_BIT),
41 .PSEN(GND_BIT),
42 .PSINCDEC(GND_BIT),
43 .RST(RST_IN),
44 .CLKDV(),
45 .CLKFX(CLKFX_BUF),
46 .CLKFX180(),
47 .CLK0(CLK0_BUF),
48 .CLK2X(),
49 .CLK2X180(),
50 .CLK90(),
51 .CLK180(),
52 .CLK270(),
53 .LOCKED(LOCKED_OUT),
54 .PSDONE(),
55 .STATUS());
56 defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
57 defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
58 defparam DCM_SP_INST.CLKFX_DIVIDE = 27;
59 defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
60 defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
61 defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;
62 defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
63 defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
64 defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
65 defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
66 defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
67 defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
68 defparam DCM_SP_INST.PHASE_SHIFT = 0;
69 defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
70 endmodule
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