update T80 ip

[fpga-games] / galaxian / t80_ip / T80_Reg.vhd

diff --git a/galaxian/t80_ip/T80_Reg.vhd b/galaxian/t80_ip/T80_Reg.vhd
index 828485fbfb04e90f9205540367f51f7cac46a56f..1c0f26384492b79c74105a1edb40fd5030c7c932 100644 (file)
--- a/galaxian/t80_ip/T80_Reg.vhd
+++ b/galaxian/t80_ip/T80_Reg.vhd
@@ -1,3 +1,12 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
 --
 -- T80 Registers, technology independent
 --
@@ -38,15 +47,15 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---     http://www.opencores.org/cvsweb.shtml/t51/
+--      http://www.opencores.org/cvsweb.shtml/t51/
 --
 -- Limitations :
 --
 -- File history :
 --
---     0242 : Initial release
+--      0242 : Initial release
 --
---     0244 : Changed to single register file
+--      0244 : Changed to single register file
 --
 
 library IEEE;
@@ -55,29 +64,29 @@ use IEEE.numeric_std.all;
 
 entity T80_Reg is
        port(
-               Clk                     : in std_logic;
-               CEN                     : in std_logic;
-               WEH                     : in std_logic;
-               WEL                     : in std_logic;
-               AddrA           : in std_logic_vector(2 downto 0);
-               AddrB           : in std_logic_vector(2 downto 0);
-               AddrC           : in std_logic_vector(2 downto 0);
-               DIH                     : in std_logic_vector(7 downto 0);
-               DIL                     : in std_logic_vector(7 downto 0);
-               DOAH            : out std_logic_vector(7 downto 0);
-               DOAL            : out std_logic_vector(7 downto 0);
-               DOBH            : out std_logic_vector(7 downto 0);
-               DOBL            : out std_logic_vector(7 downto 0);
-               DOCH            : out std_logic_vector(7 downto 0);
-               DOCL            : out std_logic_vector(7 downto 0)
+               Clk                     : in std_logic;
+               CEN                     : in std_logic;
+               WEH                     : in std_logic;
+               WEL                     : in std_logic;
+               AddrA           : in std_logic_vector(2 downto 0);
+               AddrB           : in std_logic_vector(2 downto 0);
+               AddrC           : in std_logic_vector(2 downto 0);
+               DIH                     : in std_logic_vector(7 downto 0);
+               DIL                     : in std_logic_vector(7 downto 0);
+               DOAH            : out std_logic_vector(7 downto 0);
+               DOAL            : out std_logic_vector(7 downto 0);
+               DOBH            : out std_logic_vector(7 downto 0);
+               DOBL            : out std_logic_vector(7 downto 0);
+               DOCH            : out std_logic_vector(7 downto 0);
+               DOCL            : out std_logic_vector(7 downto 0)
        );
 end T80_Reg;
 
 architecture rtl of T80_Reg is
 
        type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-       signal  RegsH   : Register_Image(0 to 7);
-       signal  RegsL   : Register_Image(0 to 7);
+       signal      RegsH   : Register_Image(0 to 7);
+       signal      RegsL   : Register_Image(0 to 7);
 
 begin