module galaxian_roms(
-I_CLK_18432M,
-I_CLK_12M,
+I_ROM_CLK,
I_ADDR,
O_DATA
);
-input I_CLK_18432M;
-input I_CLK_12M;
+input I_ROM_CLK;
input [18:0]I_ADDR;
output [7:0]O_DATA;
wire [7:0]U_ROM_D;
GALAXIAN_U U_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(U_ROM_D),
.ENA(1'b1)
wire [7:0]V_ROM_D;
GALAXIAN_V V_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(V_ROM_D),
.ENA(1'b1)
wire [7:0]W_ROM_D;
GALAXIAN_W W_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(W_ROM_D),
.ENA(1'b1)
wire [7:0]Y_ROM_D;
GALAXIAN_Y Y_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(Y_ROM_D),
.ENA(1'b1)
wire [7:0]L_ROM_D;
GALAXIAN_7L L_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(L_ROM_D),
.ENA(1'b1)
wire [7:0]K_ROM_D;
GALAXIAN_1K K_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(K_ROM_D),
.ENA(1'b1)
wire [7:0]H_ROM_D;
GALAXIAN_1H H_ROM(
-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),
.ADDR(I_ADDR[10:0]),
.DATA(H_ROM_D),
.ENA(1'b1)
// 0x04000 - 0x047FF 1k.bin VID-ROM
// 0x05000 - 0x057FF 1h.bin VID-ROM
// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
-always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
+always@(posedge I_ROM_CLK)
begin
if (I_ADDR <= 18'h7ff) begin
//u
DATA_OUT <= 8'h00;
end
else begin
- DATA_OUT <= 8'h00;
+ DATA_OUT <= DATA_OUT;
end
end
-always@(negedge I_CLK_18432M)
-begin
- DATA_OUT2 <= DATA_OUT;
-end
-
-assign O_DATA = DATA_OUT2;
+assign O_DATA = DATA_OUT;
endmodule