I_CLK_18M,\r
I_CLK_12M,\r
I_CLK_6M,\r
+I_CLK_6Mn,\r
I_H_CNT,\r
I_V_CNT,\r
I_H_FLIP,\r
input I_CLK_18M;\r
input I_CLK_12M;\r
input I_CLK_6M;\r
+input I_CLK_6Mn;\r
input [8:0]I_H_CNT;\r
input [7:0]I_V_CNT;\r
input I_H_FLIP;\r
wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
\r
reg [7:0]W_H_POSI;\r
-always@(posedge I_CLK_6M) W_H_POSI <= W_OBJ_RAM_DOB;\r
+always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
\r
mc_obj_ram OBJ_RAM(\r
\r
\r
.I_CLK(I_CLK_18M),\r
.I_ADDR(W_LRAM_A),\r
-.I_WE(I_CLK_6M),\r
+.I_WE(I_CLK_6Mn),\r
.I_D(W_LRAM_DI),\r
.O_Dn(W_LRAM_DO)\r
\r