fix object position

[fpga-games] / galaxian / src / mc_video.v

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index c93b557cc3e1a6385d9078dc1fab460ae2c46f04..c5af5e9645483c4888d1d26a4a1d3935856420cb 100644 (file)
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -45,10 +45,6 @@ I_OBJ_RAM_WRn,
 I_VID_RAM_RDn,\r
 I_VID_RAM_WRn,\r
 \r
 I_VID_RAM_RDn,\r
 I_VID_RAM_WRn,\r
 \r

-O_OBJ_ROM_A,\r
-I_OBJ_ROM_A_D,\r
-I_OBJ_ROM_B_D,\r
-\r

 O_C_BLnX,\r
 O_8HF,\r
 O_256HnX,\r
 O_C_BLnX,\r
 O_8HF,\r
 O_256HnX,\r


@@ -80,10 +76,6 @@ input  I_OBJ_RAM_WRn;
 input  I_VID_RAM_RDn;\r
 input  I_VID_RAM_WRn;\r
 \r
 input  I_VID_RAM_RDn;\r
 input  I_VID_RAM_WRn;\r
 \r

-output [10:0]O_OBJ_ROM_A;\r
-input  [7:0]I_OBJ_ROM_A_D;\r
-input  [7:0]I_OBJ_ROM_B_D;\r
-\r

 output O_C_BLnX;\r
 output O_8HF;\r
 output O_256HnX;\r
 output O_C_BLnX;\r
 output O_8HF;\r
 output O_256HnX;\r


@@ -127,7 +119,7 @@ end
 \r
 mc_ld_pls LD_PLS(\r
 \r
 \r
 mc_ld_pls LD_PLS(\r
 \r

-.I_CLK_6M(~I_CLK_6M),\r
+.I_CLK_6M(I_CLK_6M),\r

 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r
 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r


@@ -163,7 +155,7 @@ wire   [7:0]W_OBJ_RAM_A  = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;
 wire   [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
 \r
 reg    [7:0]W_H_POSI;\r
 wire   [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
 \r
 reg    [7:0]W_H_POSI;\r

-always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
+always@(posedge I_CLK_6M) W_H_POSI <= W_OBJ_RAM_DOB;\r

 \r
 mc_obj_ram OBJ_RAM(\r
 \r
 \r
 mc_obj_ram OBJ_RAM(\r
 \r


@@ -243,10 +235,27 @@ wire   [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};
 \r
 wire   [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
 \r
 \r
 wire   [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
 \r

-assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
+wire   [10:0]W_O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
+\r
+wire   [7:0]W_1K_D;\r
+wire   [7:0]W_1H_D;\r
+\r
+//1K VID-Rom\r
+GALAXIAN_1K K_ROM(\r
+.CLK(I_CLK_12M),\r
+.ADDR(W_O_OBJ_ROM_A),\r
+.DATA(W_1K_D),\r
+.ENA(1'b1)\r
+);\r
+\r
+//1H VID-Rom\r
+GALAXIAN_1H H_ROM(\r
+.CLK(I_CLK_12M),\r
+.ADDR(W_O_OBJ_ROM_A),\r
+.DATA(W_1H_D),\r
+.ENA(1'b1)\r
+);\r

 \r
 \r

-wire   [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
-wire   [7:0]W_1H_D = I_OBJ_ROM_B_D;\r

 \r
 //---------------------------------------------------------------------------------\r
 wire   W_2L_Qa,W_2K_Qd;\r
 \r
 //---------------------------------------------------------------------------------\r
 wire   W_2L_Qa,W_2K_Qd;\r


@@ -330,16 +339,14 @@ begin
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r

-wire   W_LRAM_WE = ~I_CLK_6M;\r

 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r
 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r

-wire   W_1U_CLK = ~I_CLK_6M;\r

 \r
 \r

-always@(posedge W_1U_CLK)\r
+always@(negedge I_CLK_6M)\r

 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r
 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r


@@ -370,7 +377,7 @@ mc_lram LRAM(
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r

-.I_WE(W_LRAM_WE),\r
+.I_WE(I_CLK_6M),\r

 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r
 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r