reg W_6S1_Q,W_6S1_Qn;\r
reg W_6S2_Qn;\r
\r
-//assign O_WAITn = W_6S1_Qn;\r
-assign O_WAITn = 1'b1 ; // No Wait\r
+assign O_WAITn = W_6S1_Qn;\r
+//assign O_WAITn = 1'b1 ; // No Wait\r
\r
always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
begin\r
assign O_V_FLIP = W_9N_Q[7]; // \r
\r
\r
-endmodule
\ No newline at end of file
+endmodule\r