impact 11 renamed the intel flash...

[fpga-games] / galaxian / src / mc_clock.v

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 43cadb42e86b73f13c84ee474619f0163bfd20f5..b859754fca7794335daf7700452e6b35e1c475fa 100644 (file)
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -17,47 +17,79 @@
 \r
 module mc_clock(\r
 \r
-I_CLK_18M,\r
+I_CLK_36M,\r
+I_DCM_LOCKED,\r
+O_CLK_18M,\r
 O_CLK_12M,\r
 O_CLK_06M,\r
 O_CLK_06Mn\r
 \r
 );\r
 \r
-input  I_CLK_18M;\r
+input I_CLK_36M;\r
+input I_DCM_LOCKED;\r
+output O_CLK_18M;\r
 output O_CLK_12M;\r
 output O_CLK_06M;\r
 output O_CLK_06Mn;\r
 \r
 // 2/3 clock divider(duty 33%)\r
-reg [1:0] clk_ff1,clk_ff2;\r
 //I_CLK   1010101010101010101\r
 //c_ff10  0011110011110011110\r
 //c_ff11  0011000011000011000\r
 //c_ff20  0000110000110000110\r
 //c_ff21  0110000110000110000\r
 //O_12M   0000110110110110110\r
-always @(posedge I_CLK_18M)\r
+reg [1:0] state;\r
+reg clk_12m;\r
+initial state = 0;\r
+initial clk_12m = 0;\r
+\r
+// 2/3 clock         (duty 66%)\r
+always @(posedge I_CLK_36M)\r
 begin\r
-   clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];\r
-   clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
-   clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];\r
+   if (I_DCM_LOCKED == 1) begin\r
+      case (state)\r
+         2'd0: state <= 2'd1;\r
+         2'd1: state <= 2'd2;\r
+         2'd2: state <= 2'd0;\r
+         2'd3: state <= 2'd0;\r
+      endcase\r
+\r
+      if (state == 2'd2)\r
+         clk_12m = 0;\r
+      else\r
+         clk_12m = 1;\r
+   end\r
+   else begin\r
+      state <= 2'd0;\r
+      clk_12m = 0;\r
+   end\r
 end\r
-always @(negedge I_CLK_18M)\r
-   clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
 \r
-// 2/3 clock         (duty 66%)\r
-assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];\r
- \r
+assign O_CLK_12M = clk_12m;\r
+\r
+reg CLK_18M;\r
+always @(posedge I_CLK_36M)\r
+begin\r
+   if (I_DCM_LOCKED == 1)\r
+      CLK_18M <= ~ CLK_18M;\r
+   else\r
+      CLK_18M <= 0;\r
+end\r
+assign O_CLK_18M = CLK_18M;\r
+\r
 // 1/3 clock divider (duty 50%)\r
-reg CLK_6M , CLK_6Mn;\r
+reg CLK_6M;\r
+reg CLK_6Mn;\r
+\r
 always @(posedge O_CLK_12M)\r
 begin\r
-   CLK_6Mn <=  CLK_6M;\r
    CLK_6M  <= ~CLK_6M;\r
+   CLK_6Mn <= CLK_6M;\r
 end\r
+\r
 assign O_CLK_06M = CLK_6M;\r
 assign O_CLK_06Mn = CLK_6Mn;\r
 \r
-\r
-endmodule
\ No newline at end of file
+endmodule\r