wire W_CLK_36M;\r
wire W_CLK_12M,WB_CLK_12M;\r
wire W_CLK_6M,WB_CLK_6M;\r
+wire W_CLK_6Mn;\r
wire W_STARS_CLK;\r
\r
mc_dcm clockgen(\r
.I_CLK_36M(W_CLK_36M),\r
.O_CLK_18M(W_CLK_18M),\r
.O_CLK_12M(WB_CLK_12M),\r
-.O_CLK_06M(WB_CLK_6M)\r
+.O_CLK_06M(WB_CLK_6M),\r
+.O_CLK_06Mn(W_CLK_6Mn)\r
\r
);\r
\r
.I_CLK_18M(W_CLK_18M),\r
.I_CLK_12M(W_CLK_12M),\r
.I_CLK_6M(W_CLK_6M),\r
+.I_CLK_6Mn(W_CLK_6Mn),\r
.I_H_CNT(W_H_CNT),\r
.I_V_CNT(W_V_CNT),\r
.I_H_FLIP(W_H_FLIP),\r