initial clk_12m = 0;\r
\r
// 2/3 clock (duty 66%)\r
-always @(negedge I_CLK_36M)\r
+always @(posedge I_CLK_36M)\r
begin\r
case (state)\r
2'd0: state <= 2'd1;\r
endcase\r
\r
if (state == 2'd2)\r
- clk_12m = 1;\r
- else\r
clk_12m = 0;\r
+ else\r
+ clk_12m = 1;\r
end\r
\r
assign O_CLK_12M = clk_12m;\r