impact 11 renamed the intel flash...

[fpga-games] / galaxian / src / mc_video.v

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index aafdcd3103b589173affb40fbb0f0f823cfa892c..84f23976161634881be90447402da1a573820001 100644 (file)
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -29,6 +29,7 @@ module mc_video(
 I_CLK_18M,\r
 I_CLK_12M,\r
 I_CLK_6M,\r
+I_CLK_6Mn,\r
 I_H_CNT,\r
 I_V_CNT,\r
 I_H_FLIP,\r
@@ -45,10 +46,6 @@ I_OBJ_RAM_WRn,
 I_VID_RAM_RDn,\r
 I_VID_RAM_WRn,\r
 \r
-O_OBJ_ROM_A,\r
-I_OBJ_ROM_A_D,\r
-I_OBJ_ROM_B_D,\r
-\r
 O_C_BLnX,\r
 O_8HF,\r
 O_256HnX,\r
@@ -64,6 +61,7 @@ O_COL
 input  I_CLK_18M;\r
 input  I_CLK_12M;\r
 input  I_CLK_6M;\r
+input  I_CLK_6Mn;\r
 input  [8:0]I_H_CNT;\r
 input  [7:0]I_V_CNT;\r
 input  I_H_FLIP;\r
@@ -80,10 +78,6 @@ input  I_OBJ_RAM_WRn;
 input  I_VID_RAM_RDn;\r
 input  I_VID_RAM_WRn;\r
 \r
-output [10:0]O_OBJ_ROM_A;\r
-input  [7:0]I_OBJ_ROM_A_D;\r
-input  [7:0]I_OBJ_ROM_B_D;\r
-\r
 output O_C_BLnX;\r
 output O_8HF;\r
 output O_256HnX;\r
@@ -127,7 +121,7 @@ end
 \r
 mc_ld_pls LD_PLS(\r
 \r
-.I_CLK_6M(~I_CLK_6M),\r
+.I_CLK_6M(I_CLK_6M),\r
 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r
@@ -148,7 +142,7 @@ wire   [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};
 wire   [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
 \r
 assign O_8HF = W_HF_CNT[3];\r
-assign O_1VF = I_V_CNT[0]^1'b1; //XXX: breaks when flipped\r
+assign O_1VF = W_VF_CNT[0];\r
 \r
 reg    [7:0]W_OBJ_D;\r
 wire   [3:0]W_6J_DA = {I_H_FLIP  ,           W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
@@ -243,10 +237,27 @@ wire   [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};
 \r
 wire   [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
 \r
-assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
+wire   [10:0]W_O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
+\r
+wire   [7:0]W_1K_D;\r
+wire   [7:0]W_1H_D;\r
+\r
+//1K VID-Rom\r
+GALAXIAN_1K K_ROM(\r
+.CLK(I_CLK_12M),\r
+.ADDR(W_O_OBJ_ROM_A),\r
+.DATA(W_1K_D),\r
+.ENA(1'b1)\r
+);\r
+\r
+//1H VID-Rom\r
+GALAXIAN_1H H_ROM(\r
+.CLK(I_CLK_12M),\r
+.ADDR(W_O_OBJ_ROM_A),\r
+.DATA(W_1H_D),\r
+.ENA(1'b1)\r
+);\r
 \r
-wire   [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
-wire   [7:0]W_1H_D = I_OBJ_ROM_B_D;\r
 \r
 //---------------------------------------------------------------------------------\r
 wire   W_2L_Qa,W_2K_Qd;\r
@@ -330,16 +341,14 @@ begin
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
-wire   W_LRAM_WE = ~I_CLK_6M;\r
 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r
-wire   W_1U_CLK = ~I_CLK_6M;\r
 \r
-always@(posedge W_1U_CLK)\r
+always@(negedge I_CLK_6M)\r
 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r
@@ -370,7 +379,7 @@ mc_lram LRAM(
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r
-.I_WE(W_LRAM_WE),\r
+.I_WE(I_CLK_6Mn),\r
 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r