faster clock for roms

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 5f123fda4d1f0a97d212e1f26ce1e2b74e11f5e5..853c7ed3a47df3e6bc26154d66330eb92cd1f637 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -107,11 +107,13 @@ wire   I_CLK_18432M;
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r

+wire   W_ROM_CLK;\r

 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r

-.CLKFX_OUT(I_CLK_18432M)\r
+.CLKFX_OUT(I_CLK_18432M),\r
+.CLK0_OUT(W_ROM_CLK)\r

 );\r
 \r
 //------ H&V COUNTER -------------------------\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r


@@ -425,8 +427,7 @@ wire   [7:0]ROM_D; // = I_ROM_DB;
 //assign O_ROM_WEn = 1'b1;\r
 \r
 galaxian_roms ROMS(\r
 //assign O_ROM_WEn = 1'b1;\r
 \r
 galaxian_roms ROMS(\r

-.I_CLK_18432M(I_CLK_18432M),\r
-.I_CLK_12M(WB_CLK_12M),\r
+.I_ROM_CLK(W_ROM_CLK),\r

 .I_ADDR(ROM_A),\r
 .O_DATA(ROM_D)\r
 );\r
 .I_ADDR(ROM_A),\r
 .O_DATA(ROM_D)\r
 );\r

diff --git a/galaxian/src/roms.v b/galaxian/src/roms.v
index bdaf1306ab77f72c5d9bc7b669bb3f82bcb13087..4fcf3620308f6937ff17b892d206bfc49eb0d0b3 100644 (file)
--- a/galaxian/src/roms.v
+++ b/galaxian/src/roms.v
@@ -1,12 +1,10 @@
 module galaxian_roms(
 module galaxian_roms(

-I_CLK_18432M,
-I_CLK_12M,
+I_ROM_CLK,

 I_ADDR,
 O_DATA
 );
 
 I_ADDR,
 O_DATA
 );
 

-input I_CLK_18432M;
-input I_CLK_12M;
+input I_ROM_CLK;

 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 
 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 


@@ -14,7 +12,7 @@ output [7:0]O_DATA;
 wire [7:0]U_ROM_D;
 
 GALAXIAN_U U_ROM(
 wire [7:0]U_ROM_D;
 
 GALAXIAN_U U_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(U_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(U_ROM_D),
 .ENA(1'b1)


@@ -23,7 +21,7 @@ GALAXIAN_U U_ROM(
 wire [7:0]V_ROM_D;
 
 GALAXIAN_V V_ROM(
 wire [7:0]V_ROM_D;
 
 GALAXIAN_V V_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(V_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(V_ROM_D),
 .ENA(1'b1)


@@ -32,7 +30,7 @@ GALAXIAN_V V_ROM(
 wire [7:0]W_ROM_D;
 
 GALAXIAN_W W_ROM(
 wire [7:0]W_ROM_D;
 
 GALAXIAN_W W_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(W_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(W_ROM_D),
 .ENA(1'b1)


@@ -41,7 +39,7 @@ GALAXIAN_W W_ROM(
 wire [7:0]Y_ROM_D;
 
 GALAXIAN_Y Y_ROM(
 wire [7:0]Y_ROM_D;
 
 GALAXIAN_Y Y_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(Y_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(Y_ROM_D),
 .ENA(1'b1)


@@ -51,7 +49,7 @@ GALAXIAN_Y Y_ROM(
 wire [7:0]L_ROM_D;
 
 GALAXIAN_7L L_ROM(
 wire [7:0]L_ROM_D;
 
 GALAXIAN_7L L_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(L_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(L_ROM_D),
 .ENA(1'b1)


@@ -61,7 +59,7 @@ GALAXIAN_7L L_ROM(
 wire [7:0]K_ROM_D;
 
 GALAXIAN_1K K_ROM(
 wire [7:0]K_ROM_D;
 
 GALAXIAN_1K K_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(K_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(K_ROM_D),
 .ENA(1'b1)


@@ -71,7 +69,7 @@ GALAXIAN_1K K_ROM(
 wire [7:0]H_ROM_D;
 
 GALAXIAN_1H H_ROM(
 wire [7:0]H_ROM_D;
 
 GALAXIAN_1H H_ROM(

-.CLK(I_CLK_12M),
+.CLK(I_ROM_CLK),

 .ADDR(I_ADDR[10:0]),
 .DATA(H_ROM_D),
 .ENA(1'b1)
 .ADDR(I_ADDR[10:0]),
 .DATA(H_ROM_D),
 .ENA(1'b1)


@@ -90,7 +88,7 @@ reg [7:0]DATA_OUT2;
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data

-always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
+always@(posedge I_ROM_CLK)

 begin
        if (I_ADDR <= 18'h7ff) begin
                //u
 begin
        if (I_ADDR <= 18'h7ff) begin
                //u


@@ -129,11 +127,6 @@ begin
        end
 end
 
        end
 end
 

-always@(negedge I_CLK_18432M)
-begin
-       DATA_OUT2 <= DATA_OUT;
-end
-
-assign O_DATA = DATA_OUT2;
+assign O_DATA = DATA_OUT;

 
 endmodule
 
 endmodule