fix rom address decoder

diff --git a/galaxian/galaxian.ucf b/galaxian/galaxian.ucf
index 3a8e0118a815c08483a9cfb3676b8a3a3707b44d..44165bb04c678a198b7d4749651b17c1ca8932d0 100644 (file)
--- a/galaxian/galaxian.ucf
+++ b/galaxian/galaxian.ucf
@@ -1,5 +1,11 @@
-### UCF file for FPGA-MOONCRST on XC2S200E
-#
+CONFIG PART = XC3SD1800A-FG676-4;
+
+NET I_CLK_125M TNM_NET = clk_ref_grp;
+TIMESPEC TS01 = PERIOD : clk_ref_grp : 8.00 : PRIORITY 1; #125 MHz
+
+TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns;
+TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns;
+

 #---------- MasterClock 18.432MHz ----------
 NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33;
 #-------------------------------------------
 #---------- MasterClock 18.432MHz ----------
 NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33;
 #-------------------------------------------

diff --git a/galaxian/src/dcm.v b/galaxian/src/dcm.v
index 13f9f5fc414327cc22159b72a4d43f52739696f9..64541bcaca24aa1c5a006d4b1e19d73c037af158 100644 (file)
--- a/galaxian/src/dcm.v
+++ b/galaxian/src/dcm.v
@@ -1,11 +1,11 @@
-// Module dcm
+// Module mc_dcm

 // Generated by Xilinx Architecture Wizard
 // Written for synthesis tool: XST
 // Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
 // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
 `timescale 1ns / 1ps
 
 // Generated by Xilinx Architecture Wizard
 // Written for synthesis tool: XST
 // Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
 // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
 `timescale 1ns / 1ps
 

-module dcm(CLKIN_IN, 
+module mc_dcm(CLKIN_IN, 

            RST_IN, 
            CLKFX_OUT, 
            CLKIN_IBUFG_OUT, 
            RST_IN, 
            CLKFX_OUT, 
            CLKIN_IBUFG_OUT, 

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index c382b640ee6ffd53a20bce5f67cb8093cd51cac8..d8508d1a521f01e0587766d80bc209ff7ff91674 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -108,7 +108,7 @@ wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r
 \r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r
 \r

-dcm clockgen(\r
+mc_dcm clockgen(\r

 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
 .CLKFX_OUT(I_CLK_18432M)\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
 .CLKFX_OUT(I_CLK_18432M)\r


@@ -425,7 +425,6 @@ wire   [7:0]ROM_D; // = I_ROM_DB;
 //assign O_ROM_WEn = 1'b1;\r
 \r
 galaxian_roms ROMS(\r
 //assign O_ROM_WEn = 1'b1;\r
 \r
 galaxian_roms ROMS(\r

-.I_CLK_18432M(I_CLK_18432M),\r

 .I_CLK_12M(WB_CLK_12M),\r
 .I_ADDR(ROM_A),\r
 .O_DATA(ROM_D)\r
 .I_CLK_12M(WB_CLK_12M),\r
 .I_ADDR(ROM_A),\r
 .O_DATA(ROM_D)\r

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index aafdcd3103b589173affb40fbb0f0f823cfa892c..c93b557cc3e1a6385d9078dc1fab460ae2c46f04 100644 (file)
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -148,7 +148,7 @@ wire   [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};
 wire   [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
 \r
 assign O_8HF = W_HF_CNT[3];\r
 wire   [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
 \r
 assign O_8HF = W_HF_CNT[3];\r

-assign O_1VF = I_V_CNT[0]^1'b1; //XXX: breaks when flipped\r
+assign O_1VF = W_VF_CNT[0];\r

 \r
 reg    [7:0]W_OBJ_D;\r
 wire   [3:0]W_6J_DA = {I_H_FLIP  ,           W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
 \r
 reg    [7:0]W_OBJ_D;\r
 wire   [3:0]W_6J_DA = {I_H_FLIP  ,           W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r

diff --git a/galaxian/src/roms.v b/galaxian/src/roms.v
index 02c0bd2ea199f73264e2e095348e6bec573d0a41..2ca0d07c7e0c4c96fd81aa991158a6ad04b9dc6d 100644 (file)
--- a/galaxian/src/roms.v
+++ b/galaxian/src/roms.v
@@ -1,85 +1,76 @@
 module galaxian_roms(
 module galaxian_roms(

-I_CLK_18432M,

 I_CLK_12M,
 I_ADDR,
 O_DATA
 );
 
 input I_CLK_12M;
 I_CLK_12M,
 I_ADDR,
 O_DATA
 );
 
 input I_CLK_12M;

-input I_CLK_18432M;

 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 
 //CPU-Roms
 wire [7:0]U_ROM_D;
 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 
 //CPU-Roms
 wire [7:0]U_ROM_D;

-reg [10:0]U_ROM_A;

 
 GALAXIAN_U U_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_U U_ROM(
 .CLK(I_CLK_12M),

-.ADDR(U_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(U_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]V_ROM_D;
 .DATA(U_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]V_ROM_D;

-reg [10:0]V_ROM_A;

 
 GALAXIAN_V V_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_V V_ROM(
 .CLK(I_CLK_12M),

-.ADDR(V_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(V_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]W_ROM_D;
 .DATA(V_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]W_ROM_D;

-reg [10:0]W_ROM_A;

 
 GALAXIAN_W W_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_W W_ROM(
 .CLK(I_CLK_12M),

-.ADDR(W_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(W_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]Y_ROM_D;
 .DATA(W_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]Y_ROM_D;

-reg [10:0]Y_ROM_A;

 
 GALAXIAN_Y Y_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_Y Y_ROM(
 .CLK(I_CLK_12M),

-.ADDR(Y_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(Y_ROM_D),
 .ENA(1'b1)
 );
 
 //7L CPU-Rom
 wire [7:0]L_ROM_D;
 .DATA(Y_ROM_D),
 .ENA(1'b1)
 );
 
 //7L CPU-Rom
 wire [7:0]L_ROM_D;

-reg [10:0]L_ROM_A;

 
 GALAXIAN_7L L_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_7L L_ROM(
 .CLK(I_CLK_12M),

-.ADDR(L_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(L_ROM_D),
 .ENA(1'b1)
 );
 
 //1K VID-Rom
 wire [7:0]K_ROM_D;
 .DATA(L_ROM_D),
 .ENA(1'b1)
 );
 
 //1K VID-Rom
 wire [7:0]K_ROM_D;

-reg [10:0]K_ROM_A;

 
 GALAXIAN_1K K_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_1K K_ROM(
 .CLK(I_CLK_12M),

-.ADDR(K_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(K_ROM_D),
 .ENA(1'b1)
 );
 
 //1H VID-Rom
 wire [7:0]H_ROM_D;
 .DATA(K_ROM_D),
 .ENA(1'b1)
 );
 
 //1H VID-Rom
 wire [7:0]H_ROM_D;

-reg [10:0]H_ROM_A;

 
 GALAXIAN_1H H_ROM(
 .CLK(I_CLK_12M),
 
 GALAXIAN_1H H_ROM(
 .CLK(I_CLK_12M),

-.ADDR(H_ROM_A),
+.ADDR(I_ADDR[10:0]),

 .DATA(H_ROM_D),
 .ENA(1'b1)
 );
 .DATA(H_ROM_D),
 .ENA(1'b1)
 );


@@ -96,47 +87,43 @@ reg [7:0]DATA_OUT;
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data

-always
+always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)

 begin
        if (I_ADDR <= 18'h7ff) begin
                //u
 begin
        if (I_ADDR <= 18'h7ff) begin
                //u

-               U_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= U_ROM_D;
        end
                DATA_OUT <= U_ROM_D;
        end

-       if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
+       else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin

                //v
                //v

-               V_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= V_ROM_D;
        end
                DATA_OUT <= V_ROM_D;
        end

-       if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
+       else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin

                //w
                //w

-               W_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= W_ROM_D;
        end
                DATA_OUT <= W_ROM_D;
        end

-       if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
+       else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin

                //y
                //y

-               Y_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= Y_ROM_D;
        end
                DATA_OUT <= Y_ROM_D;
        end

-       if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
+       else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin

                //7l
                //7l

-               L_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= L_ROM_D;
        end
                DATA_OUT <= L_ROM_D;
        end

-       if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
+       else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin

                //1k
                //1k

-               K_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= K_ROM_D;
        end
                DATA_OUT <= K_ROM_D;
        end

-       if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
+       else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin

                //1h
                //1h

-               H_ROM_A <= I_ADDR[10:0];

                DATA_OUT <= H_ROM_D;
        end
                DATA_OUT <= H_ROM_D;
        end

-       if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
+       else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin

                //sound
                DATA_OUT <= 8'h00;
        end
                //sound
                DATA_OUT <= 8'h00;
        end

+       else begin
+               DATA_OUT <= 8'h00;
+       end

 end
 
 assign O_DATA = DATA_OUT;
 end
 
 assign O_DATA = DATA_OUT;