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Commit | Line | Data |
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47bcbf55 MG |
1 | From f8a6bbe8437ae48f5638a58472e5bb8c3f9101cf Mon Sep 17 00:00:00 2001 |
2 | From: Saeed Bishara <saeed@marvell.com> | |
3 | Date: Sun, 14 Feb 2010 18:28:46 +0200 | |
4 | Subject: [PATCH] arm: invalidate TLBs when enabling mmu | |
5 | ||
6 | ||
7 | Signed-off-by: Saeed Bishara <saeed@marvell.com> | |
8 | --- | |
9 | arch/arm/boot/compressed/head.S | 1 + | |
10 | 1 files changed, 1 insertions(+), 0 deletions(-) | |
11 | ||
12 | diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S | |
13 | index 40ef902..f421d06 100644 | |
14 | --- a/arch/arm/boot/compressed/head.S | |
15 | +++ b/arch/arm/boot/compressed/head.S | |
16 | @@ -481,6 +481,7 @@ __armv7_mmu_cache_on: | |
17 | mcr p15, 0, r0, c1, c0, 0 @ load control register | |
18 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
19 | mov r0, #0 | |
20 | + mcr p15, 0, r0, c8, c7, 0 @ invalidate I,D TLBs | |
21 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
22 | mov pc, r12 | |
23 | ||
24 | -- | |
25 | 1.6.0.4 | |
26 |