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1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
19
20 #include "proc-macros.S"
21
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32
33 #ifndef CONFIG_SMP
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
37 #else
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
41 #endif
42
43 ENTRY(cpu_v7_proc_init)
44 mov pc, lr
45 ENDPROC(cpu_v7_proc_init)
46
47 ENTRY(cpu_v7_proc_fin)
48 mov pc, lr
49 ENDPROC(cpu_v7_proc_fin)
50
51 /*
52 * cpu_v7_reset(loc)
53 *
54 * Perform a soft reset of the system. Put the CPU into the
55 * same state as it would be if it had been reset, and branch
56 * to what would be the reset vector.
57 *
58 * - loc - location to jump to for soft reset
59 *
60 * It is assumed that:
61 */
62 .align 5
63 ENTRY(cpu_v7_reset)
64 mov pc, r0
65 ENDPROC(cpu_v7_reset)
66
67 /*
68 * cpu_v7_do_idle()
69 *
70 * Idle the processor (eg, wait for interrupt).
71 *
72 * IRQs are already disabled.
73 */
74 ENTRY(cpu_v7_do_idle)
75 dsb @ WFI may enter a low-power mode
76 wfi
77 mov pc, lr
78 ENDPROC(cpu_v7_do_idle)
79
80 ENTRY(cpu_v7_dcache_clean_area)
81 #ifndef TLB_CAN_READ_FROM_L1_CACHE
82 dcache_line_size r2, r3
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, r2
85 subs r1, r1, r2
86 bhi 1b
87 dsb
88 #endif
89 mov pc, lr
90 ENDPROC(cpu_v7_dcache_clean_area)
91
92 /*
93 * cpu_v7_switch_mm(pgd_phys, tsk)
94 *
95 * Set the translation table base pointer to be pgd_phys
96 *
97 * - pgd_phys - physical address of new TTB
98 *
99 * It is assumed that:
100 * - we are not using split page tables
101 */
102 ENTRY(cpu_v7_switch_mm)
103 #ifdef CONFIG_MMU
104 mov r2, #0
105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
106 orr r0, r0, #TTB_FLAGS
107 #ifdef CONFIG_ARM_ERRATA_430973
108 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
109 #endif
110 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
111 isb
112 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 isb
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
115 isb
116 #endif
117 mov pc, lr
118 ENDPROC(cpu_v7_switch_mm)
119
120 /*
121 * cpu_v7_set_pte_ext(ptep, pte)
122 *
123 * Set a level 2 translation table entry.
124 *
125 * - ptep - pointer to level 2 translation table entry
126 * (hardware version is stored at -1024 bytes)
127 * - pte - PTE value to store
128 * - ext - value for extended PTE bits
129 */
130 ENTRY(cpu_v7_set_pte_ext)
131 #ifdef CONFIG_MMU
132 ARM( str r1, [r0], #-2048 ) @ linux version
133 THUMB( str r1, [r0] ) @ linux version
134 THUMB( sub r0, r0, #2048 )
135
136 bic r3, r1, #0x000003f0
137 bic r3, r3, #PTE_TYPE_MASK
138 orr r3, r3, r2
139 orr r3, r3, #PTE_EXT_AP0 | 2
140
141 tst r1, #1 << 4
142 orrne r3, r3, #PTE_EXT_TEX(1)
143
144 tst r1, #L_PTE_WRITE
145 tstne r1, #L_PTE_DIRTY
146 orreq r3, r3, #PTE_EXT_APX
147
148 tst r1, #L_PTE_USER
149 orrne r3, r3, #PTE_EXT_AP1
150 tstne r3, #PTE_EXT_APX
151 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
152
153 tst r1, #L_PTE_EXEC
154 orreq r3, r3, #PTE_EXT_XN
155
156 tst r1, #L_PTE_YOUNG
157 tstne r1, #L_PTE_PRESENT
158 moveq r3, #0
159
160 str r3, [r0]
161 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
162 #endif
163 mov pc, lr
164 ENDPROC(cpu_v7_set_pte_ext)
165
166 cpu_v7_name:
167 .ascii "ARMv7 Processor"
168 .align
169
170 __INIT
171
172 /*
173 * __v7_setup
174 *
175 * Initialise TLB, Caches, and MMU state ready to switch the MMU
176 * on. Return in r0 the new CP15 C1 control register setting.
177 *
178 * We automatically detect if we have a Harvard cache, and use the
179 * Harvard cache control instructions insead of the unified cache
180 * control instructions.
181 *
182 * This should be able to cover all ARMv7 cores.
183 *
184 * It is assumed that:
185 * - cache type register is implemented
186 */
187 __v7_setup:
188 #ifdef CONFIG_SMP
189 mrc p15, 0, r0, c1, c0, 1
190 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
191 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
192 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
193 #endif
194 adr r12, __v7_setup_stack @ the local stack
195 stmia r12, {r0-r5, r7, r9, r11, lr}
196 bl v7_flush_dcache_all
197 ldmia r12, {r0-r5, r7, r9, r11, lr}
198
199 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
200 and r10, r0, #0xff000000 @ ARM?
201 teq r10, #0x41000000
202 bne 2f
203 and r5, r0, #0x00f00000 @ variant
204 and r6, r0, #0x0000000f @ revision
205 orr r0, r6, r5, lsr #20-4 @ combine variant and revision
206
207 #ifdef CONFIG_ARM_ERRATA_430973
208 teq r5, #0x00100000 @ only present in r1p*
209 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
210 orreq r10, r10, #(1 << 6) @ set IBE to 1
211 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
212 #endif
213 #ifdef CONFIG_ARM_ERRATA_458693
214 teq r0, #0x20 @ only present in r2p0
215 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
216 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
217 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
218 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
219 #endif
220 #ifdef CONFIG_ARM_ERRATA_460075
221 teq r0, #0x20 @ only present in r2p0
222 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
223 tsteq r10, #1 << 22
224 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
225 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
226 #endif
227
228 2: mov r10, #0
229 #ifdef HARVARD_CACHE
230 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
231 #endif
232 dsb
233 #ifdef CONFIG_MMU
234 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
235 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
236 orr r4, r4, #TTB_FLAGS
237 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
238 mov r10, #0x1f @ domains 0, 1 = manager
239 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
240 /*
241 * Memory region attributes with SCTLR.TRE=1
242 *
243 * n = TEX[0],C,B
244 * TR = PRRR[2n+1:2n] - memory type
245 * IR = NMRR[2n+1:2n] - inner cacheable property
246 * OR = NMRR[2n+17:2n+16] - outer cacheable property
247 *
248 * n TR IR OR
249 * UNCACHED 000 00
250 * BUFFERABLE 001 10 00 00
251 * WRITETHROUGH 010 10 10 10
252 * WRITEBACK 011 10 11 11
253 * reserved 110
254 * WRITEALLOC 111 10 01 01
255 * DEV_SHARED 100 01
256 * DEV_NONSHARED 100 01
257 * DEV_WC 001 10
258 * DEV_CACHED 011 10
259 *
260 * Other attributes:
261 *
262 * DS0 = PRRR[16] = 0 - device shareable property
263 * DS1 = PRRR[17] = 1 - device shareable property
264 * NS0 = PRRR[18] = 0 - normal shareable property
265 * NS1 = PRRR[19] = 1 - normal shareable property
266 * NOS = PRRR[24+n] = 1 - not outer shareable
267 */
268 ldr r5, =0xff0a81a8 @ PRRR
269 ldr r6, =0x40e040e0 @ NMRR
270 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
271 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
272 #endif
273 adr r5, v7_crval
274 ldmia r5, {r5, r6}
275 #ifdef CONFIG_CPU_ENDIAN_BE8
276 orr r6, r6, #1 << 25 @ big-endian page tables
277 #endif
278 mrc p15, 0, r0, c1, c0, 0 @ read control register
279 bic r0, r0, r5 @ clear bits them
280 orr r0, r0, r6 @ set them
281 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
282 mov pc, lr @ return to head.S:__ret
283 ENDPROC(__v7_setup)
284
285 /* AT
286 * TFR EV X F I D LR S
287 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
288 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
289 * 1 0 110 0011 1100 .111 1101 < we want
290 */
291 .type v7_crval, #object
292 v7_crval:
293 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
294
295 __v7_setup_stack:
296 .space 4 * 11 @ 11 registers
297
298 .type v7_processor_functions, #object
299 ENTRY(v7_processor_functions)
300 .word v7_early_abort
301 .word v7_pabort
302 .word cpu_v7_proc_init
303 .word cpu_v7_proc_fin
304 .word cpu_v7_reset
305 .word cpu_v7_do_idle
306 .word cpu_v7_dcache_clean_area
307 .word cpu_v7_switch_mm
308 .word cpu_v7_set_pte_ext
309 .size v7_processor_functions, . - v7_processor_functions
310
311 .type cpu_arch_name, #object
312 cpu_arch_name:
313 .asciz "armv7"
314 .size cpu_arch_name, . - cpu_arch_name
315
316 .type cpu_elf_name, #object
317 cpu_elf_name:
318 .asciz "v7"
319 .size cpu_elf_name, . - cpu_elf_name
320 .align
321
322 .section ".proc.info.init", #alloc, #execinstr
323
324 /*
325 * Match any ARMv7 processor core.
326 */
327 .type __v7_proc_info, #object
328 __v7_proc_info:
329 .long 0x000f0000 @ Required ID value
330 .long 0x000f0000 @ Mask for ID
331 .long PMD_TYPE_SECT | \
332 PMD_SECT_AP_WRITE | \
333 PMD_SECT_AP_READ | \
334 PMD_FLAGS
335 .long PMD_TYPE_SECT | \
336 PMD_SECT_XN | \
337 PMD_SECT_AP_WRITE | \
338 PMD_SECT_AP_READ
339 b __v7_setup
340 .long cpu_arch_name
341 .long cpu_elf_name
342 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
343 .long cpu_v7_name
344 .long v7_processor_functions
345 .long v7wbi_tlb_fns
346 .long v6_user_fns
347 .long v7_cache_fns
348 .size __v7_proc_info, . - __v7_proc_info
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