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[ms2-kexec] / omap2_serial.c
1 /*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial_reg.h>
20 #include <linux/clk.h>
21 #ifdef CONFIG_SERIAL_OMAP
22 #include <linux/platform_device.h>
23 #endif
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/debugfs.h>
27
28 #include <plat/common.h>
29 #include <plat/board.h>
30 #include <plat/clock.h>
31 #include <plat/control.h>
32 #include <mach/gpio.h>
33 #include <plat/omap-serial.h>
34
35 #include <asm/mach/serial_omap.h>
36
37 #include "prm.h"
38 #include "pm.h"
39 #include "prm-regbits-34xx.h"
40
41 #define OMAP_CTRL_REGADDR(reg) (OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE) + (reg))
42
43 void omap_ctrl_writew(u16 val, u16 offset)
44 {
45 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
46 }
47
48 u16 omap_ctrl_readw(u16 offset)
49 {
50 return __raw_readw(OMAP_CTRL_REGADDR(offset));
51 }
52
53 #define DEFAULT_TIMEOUT HZ
54
55 struct omap_uart_state {
56 int num;
57 int can_sleep;
58 struct timer_list timer;
59 u32 timeout;
60
61 void __iomem *wk_st;
62 void __iomem *wk_en;
63 u32 wk_mask;
64 u32 padconf;
65
66 u32 rts_padconf;
67 int rts_override;
68 u16 rts_padvalue;
69
70 struct clk *ick;
71 struct clk *fck;
72 int clocked;
73
74 struct plat_serialomap_port *p;
75 struct list_head node;
76
77 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
78 int context_valid;
79
80 /* Registers to be saved/restored for OFF-mode */
81 u16 dll;
82 u16 dlh;
83 u16 ier;
84 u16 sysc;
85 u16 scr;
86 u16 wer;
87 #endif
88 };
89
90 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
91 static LIST_HEAD(uart_list);
92 static unsigned int fifo_idleblks = 0;
93 static int uart0_padconf = 0x180;
94
95 static struct plat_serialomap_port serial_platform_data[] = {
96 {
97 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART1_BASE),
98 .irq = 72,
99 .regshift = 2,
100 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
101 .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
102 #endif
103 .flags = UPF_BOOT_AUTOCONF,
104 },
105 {
106 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART2_BASE),
107 .irq = 73,
108 .regshift = 2,
109 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
110 .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
111 #endif
112 .flags = UPF_BOOT_AUTOCONF,
113 },
114 {
115 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART3_BASE),
116 .irq = 74,
117 .regshift = 2,
118 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
119 .ctsrts = UART_EFR_RTS,
120 #endif
121 .flags = UPF_BOOT_AUTOCONF,
122 },
123 };
124
125 #if 0
126 static struct resource omap2_uart1_resources[] = {
127 {
128 .start = OMAP_UART1_BASE,
129 .end = OMAP_UART1_BASE + 0x3ff,
130 .flags = IORESOURCE_MEM,
131 }, {
132 .start = 72,
133 .flags = IORESOURCE_IRQ,
134 }
135 };
136
137 static struct resource omap2_uart2_resources[] = {
138 {
139 .start = OMAP_UART2_BASE,
140 .end = OMAP_UART2_BASE + 0x3ff,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = 73,
144 .flags = IORESOURCE_IRQ,
145 }
146 };
147 #endif
148
149 static struct resource omap2_uart3_resources[] = {
150 {
151 .start = OMAP_UART3_BASE,
152 .end = OMAP_UART3_BASE + 0x3ff,
153 .flags = IORESOURCE_MEM,
154 }, {
155 .start = 74,
156 .flags = IORESOURCE_IRQ,
157 }
158 };
159
160 #ifdef CONFIG_MACH_OMAP_ZOOM2
161 static struct resource omap2_quaduart_resources[] = {
162 {
163 .start = 0x10000000,
164 .end = 0x10000000 + (0x16 << 1),
165 .flags = IORESOURCE_MEM,
166 }, {
167 .start = OMAP_GPIO_IRQ(102),
168 .flags = IORESOURCE_IRQ,
169 }
170 };
171 #endif
172
173 #if 0
174 /* OMAP UART platform structure */
175 static struct platform_device uart1_device = {
176 .name = "omap-uart",
177 .id = 1,
178 .num_resources = ARRAY_SIZE(omap2_uart1_resources),
179 .resource = omap2_uart1_resources,
180 .dev.platform_data = &serial_platform_data[0],
181 };
182 static struct platform_device uart2_device = {
183 .name = "omap-uart",
184 .id = 2,
185 .num_resources = ARRAY_SIZE(omap2_uart2_resources),
186 .resource = omap2_uart2_resources,
187 .dev.platform_data = &serial_platform_data[1],
188 };
189 #endif
190 static struct platform_device uart3_device = {
191 .name = "omap-hs-uart",
192 .id = 3,
193 .num_resources = ARRAY_SIZE(omap2_uart3_resources),
194 .resource = omap2_uart3_resources,
195 .dev.platform_data = &serial_platform_data[2],
196 };
197
198 static struct platform_device *uart_devices[] = {
199 &uart3_device,
200 };
201
202 static inline unsigned int serial_read_reg(struct plat_serialomap_port *up,
203 int offset)
204 {
205 offset <<= up->regshift;
206 return (unsigned int)__raw_readb(up->membase + offset);
207 }
208
209 static inline void serial_write_reg(struct plat_serialomap_port *p, int offset,
210 int value)
211 {
212 offset <<= p->regshift;
213 __raw_writeb(value, p->membase + offset);
214 }
215
216 /*
217 * Internal UARTs need to be initialized for the 8250 autoconfig to work
218 * properly. Note that the TX watermark initialization may not be needed
219 * once the 8250.c watermark handling code is merged.
220 */
221 static inline void omap_uart_reset(struct omap_uart_state *uart)
222 {
223 struct plat_serialomap_port *p = uart->p;
224
225 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
226 serial_write_reg(p, UART_OMAP_SCR, 0x08);
227 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
228 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
229 }
230
231 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
232 {
233 if (uart->clocked)
234 return;
235
236 clk_enable(uart->ick);
237 clk_enable(uart->fck);
238 uart->clocked = 1;
239 }
240
241 #ifdef CONFIG_PM
242 #ifdef CONFIG_ARCH_OMAP3
243
244 static void omap_uart_save_context(struct omap_uart_state *uart)
245 {
246 u16 lcr = 0;
247 struct plat_serialomap_port *p = uart->p;
248
249 if (!enable_off_mode)
250 return;
251
252 /* FIXME
253 * For omap3430 CORE/PERR OFF isn't temporarily supported,
254 * so no need to save&restore the context of serial.
255 */
256 if (cpu_is_omap34xx())
257 return;
258
259 lcr = serial_read_reg(p, UART_LCR);
260 serial_write_reg(p, UART_LCR, 0xBF);
261 uart->dll = serial_read_reg(p, UART_DLL);
262 uart->dlh = serial_read_reg(p, UART_DLM);
263 serial_write_reg(p, UART_LCR, lcr);
264 uart->ier = serial_read_reg(p, UART_IER);
265 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
266 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
267 uart->wer = serial_read_reg(p, UART_OMAP_WER);
268
269 uart->context_valid = 1;
270 }
271
272 static void omap_uart_restore_context(struct omap_uart_state *uart)
273 {
274 u16 efr = 0;
275 struct plat_serialomap_port *p = uart->p;
276
277 if (!enable_off_mode)
278 return;
279
280 if (!uart->context_valid)
281 return;
282
283 /* FIXME
284 * For omap3430 CORE/PERR OFF isn't temporarily supported,
285 * so no need to save&restore the context of serial.
286 */
287 if (cpu_is_omap34xx())
288 return;
289
290 uart->context_valid = 0;
291
292 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
293 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
294 efr = serial_read_reg(p, UART_EFR);
295 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
296 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
297 serial_write_reg(p, UART_IER, 0x0);
298 #ifdef CONFIG_SERIAL_OMAP
299 serial_write_reg(p, UART_FCR, fcr[uart->num]);
300 #else
301 serial_write_reg(p, UART_FCR, 0xA1);
302 #endif
303 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
304 serial_write_reg(p, UART_DLL, uart->dll);
305 serial_write_reg(p, UART_DLM, uart->dlh);
306 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
307 serial_write_reg(p, UART_IER, uart->ier);
308 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
309 serial_write_reg(p, UART_EFR, efr);
310 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
311 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
312 serial_write_reg(p, UART_OMAP_WER, uart->wer);
313 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
314 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
315 }
316 #else
317 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
318 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
319 #endif /* CONFIG_ARCH_OMAP3 */
320
321 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
322 int enable)
323 {
324 struct plat_serialomap_port *p = uart->p;
325 u16 sysc;
326
327 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
328 if (enable)
329 sysc |= 0x2 << 3;
330 else
331 sysc |= 0x1 << 3;
332
333 serial_write_reg(p, UART_OMAP_SYSC, sysc);
334 }
335
336 static inline void omap_uart_disable_rtspullup(struct omap_uart_state *uart)
337 {
338 if (!uart->rts_padconf || !uart->rts_override)
339 return;
340 omap_ctrl_writew(uart->rts_padvalue, uart->rts_padconf);
341 uart->rts_override = 0;
342 }
343
344 static inline void omap_uart_enable_rtspullup(struct omap_uart_state *uart)
345 {
346 if (!uart->rts_padconf || uart->rts_override)
347 return;
348
349 uart->rts_padvalue = omap_ctrl_readw(uart->rts_padconf);
350 omap_ctrl_writew(0x18 | 0x7, uart->rts_padconf);
351 uart->rts_override = 1;
352 }
353
354 static inline void omap_uart_restore(struct omap_uart_state *uart)
355 {
356 omap_uart_enable_clocks(uart);
357 omap_uart_restore_context(uart);
358 }
359
360 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
361 {
362 if (!uart->clocked)
363 return;
364 omap_uart_save_context(uart);
365 uart->clocked = 0;
366 clk_disable(uart->ick);
367 clk_disable(uart->fck);
368 }
369
370 static void _omap_uart_block_sleep(struct omap_uart_state *uart)
371 {
372 omap_uart_restore(uart);
373
374 omap_uart_smart_idle_enable(uart, 0);
375 uart->can_sleep = 0;
376 if (uart->timeout)
377 mod_timer(&uart->timer, jiffies + uart->timeout);
378 else
379 del_timer(&uart->timer);
380 }
381
382 #if 0
383 static void omap_uart_block_sleep(int num)
384 {
385 struct omap_uart_state *uart;
386
387 list_for_each_entry(uart, &uart_list, node) {
388 if (num == uart->num)
389 _omap_uart_block_sleep(uart);
390 return;
391 }
392 }
393 EXPORT_SYMBOL(omap_uart_block_sleep);
394 #endif
395
396 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
397 {
398 if (!uart->clocked)
399 return;
400
401 omap_uart_smart_idle_enable(uart, 1);
402 uart->can_sleep = 1;
403 del_timer(&uart->timer);
404 }
405
406 static void omap_uart_idle_timer(unsigned long data)
407 {
408 struct omap_uart_state *uart = (struct omap_uart_state *)data;
409
410 omap_uart_allow_sleep(uart);
411 }
412
413 void omap_uart_prepare_idle(int num)
414 {
415 struct omap_uart_state *uart;
416
417 list_for_each_entry(uart, &uart_list, node) {
418 if (num == uart->num && uart->can_sleep) {
419
420 omap_uart_enable_rtspullup(uart);
421 /*
422 * There seems to be a window here where
423 * data could still be on the way to the
424 * fifo. This delay is ~1 byte time @ 115.2k
425 */
426 if (uart->num == 0)
427 udelay(80);
428
429 #ifdef CONFIG_SERIAL_OMAP
430 if (are_driveromap_uarts_active(num)) {
431 fifo_idleblks++;
432 _omap_uart_block_sleep(uart);
433 omap_uart_disable_rtspullup(uart);
434 return;
435 }
436 #endif
437 omap_uart_disable_clocks(uart);
438 return;
439 }
440 }
441 }
442
443 void omap_uart_resume_idle(int num)
444 {
445 struct omap_uart_state *uart;
446
447 list_for_each_entry(uart, &uart_list, node) {
448 if (num == uart->num) {
449 omap_uart_restore(uart);
450 omap_uart_disable_rtspullup(uart);
451
452 /* Check for IO pad wakeup */
453 if (cpu_is_omap34xx() && uart->padconf) {
454 u16 p = omap_ctrl_readw(uart->padconf);
455
456 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
457 _omap_uart_block_sleep(uart);
458 }
459
460 /* Check for normal UART wakeup */
461 if (__raw_readl(uart->wk_st) & uart->wk_mask) {
462 _omap_uart_block_sleep(uart);
463 }
464
465 return;
466 }
467 }
468 }
469
470 void omap_uart_prepare_suspend(void)
471 {
472 struct omap_uart_state *uart;
473
474 list_for_each_entry(uart, &uart_list, node) {
475 omap_uart_allow_sleep(uart);
476 }
477 }
478
479 int omap_uart_can_sleep(void)
480 {
481 struct omap_uart_state *uart;
482 int can_sleep = 1;
483
484 list_for_each_entry(uart, &uart_list, node) {
485 if (!uart->clocked)
486 continue;
487
488 if (!uart->can_sleep) {
489 can_sleep = 0;
490 continue;
491 }
492
493 #ifdef CONFIG_SERIAL_OMAP
494 if (are_driveromap_uarts_active(uart->num)) {
495 can_sleep = 0;
496 continue;
497 }
498 #endif
499
500 /* This UART can now safely sleep. */
501 omap_uart_allow_sleep(uart);
502 }
503
504 return can_sleep;
505 }
506
507 /**
508 * omap_uart_interrupt()
509 *
510 * This handler is used only to detect that *any* UART interrupt has
511 * occurred. It does _nothing_ to handle the interrupt. Rather,
512 * any UART interrupt will trigger the inactivity timer so the
513 * UART will not idle or sleep for its timeout period.
514 *
515 **/
516 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
517 {
518 struct omap_uart_state *uart = dev_id;
519
520 _omap_uart_block_sleep(uart);
521
522 return IRQ_NONE;
523 }
524
525 static u32 sleep_timeout = DEFAULT_TIMEOUT;
526
527 static void omap_uart_rtspad_init(struct omap_uart_state *uart)
528 {
529 if (!cpu_is_omap34xx())
530 return;
531 switch(uart->num) {
532 case 0:
533 uart->rts_padconf = 0x17e;
534 break;
535 case 1:
536 uart->rts_padconf = 0x176;
537 break;
538 case 2:
539 /* uart->rts_padconf = 0x19c; */
540 break;
541 default:
542 uart->rts_padconf = 0;
543 break;
544 }
545 }
546
547 static void omap_uart_idle_init(struct omap_uart_state *uart)
548 {
549 u32 v;
550 struct plat_serialomap_port *p = uart->p;
551 int ret;
552
553 uart->can_sleep = 0;
554 uart->timeout = sleep_timeout;
555 if (!uart->timeout)
556 _omap_uart_block_sleep(uart);
557 else {
558 setup_timer(&uart->timer, omap_uart_idle_timer,
559 (unsigned long) uart);
560 mod_timer(&uart->timer, jiffies + uart->timeout);
561 omap_uart_smart_idle_enable(uart, 0);
562 }
563
564 if (cpu_is_omap34xx()) {
565 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
566 u32 wk_mask = 0;
567 u32 padconf = 0;
568
569 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
570 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
571 switch (uart->num) {
572 case 0:
573 wk_mask = OMAP3430_ST_UART1_MASK;
574 padconf = uart0_padconf;
575 break;
576 case 1:
577 wk_mask = OMAP3430_ST_UART2_MASK;
578 padconf = 0x17a;
579 break;
580 case 2:
581 wk_mask = OMAP3430_ST_UART3_MASK;
582 padconf = 0x19e;
583 break;
584 }
585 uart->wk_mask = wk_mask;
586 uart->padconf = padconf;
587 } else if (cpu_is_omap24xx()) {
588 u32 wk_mask = 0;
589
590 if (cpu_is_omap2430()) {
591 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
592 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
593 } else if (cpu_is_omap2420()) {
594 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
595 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
596 }
597 switch (uart->num) {
598 case 0:
599 wk_mask = OMAP24XX_ST_UART1_MASK;
600 break;
601 case 1:
602 wk_mask = OMAP24XX_ST_UART2_MASK;
603 break;
604 case 2:
605 wk_mask = OMAP24XX_ST_UART3_MASK;
606 break;
607 }
608 uart->wk_mask = wk_mask;
609 } else {
610 uart->wk_en = 0;
611 uart->wk_st = 0;
612 uart->wk_mask = 0;
613 uart->padconf = 0;
614 }
615
616 /* Set wake-enable bit */
617 if (uart->wk_en && uart->wk_mask) {
618 v = __raw_readl(uart->wk_en);
619 v |= uart->wk_mask;
620 __raw_writel(v, uart->wk_en);
621 }
622
623 /* Ensure IOPAD wake-enables are set */
624 if (cpu_is_omap34xx() && uart->padconf) {
625 u16 v;
626
627 v = omap_ctrl_readw(uart->padconf);
628 v |= OMAP3_PADCONF_WAKEUPENABLE0;
629 omap_ctrl_writew(v, uart->padconf);
630 }
631
632 p->flags |= UPF_SHARE_IRQ;
633 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
634 "serial idle", (void *)uart);
635 WARN_ON(ret);
636 }
637
638 void omap_uart_enable_irqs(int enable)
639 {
640 int ret;
641 struct omap_uart_state *uart;
642
643 list_for_each_entry(uart, &uart_list, node) {
644 if (enable)
645 ret = request_irq(uart->p->irq, omap_uart_interrupt,
646 IRQF_SHARED, "serial idle", (void *)uart);
647 else
648 free_irq(uart->p->irq, (void *)uart);
649 }
650 }
651
652 #if 0
653 static ssize_t sleep_timeout_show(struct kobject *kobj,
654 struct kobj_attribute *attr,
655 char *buf)
656 {
657 return sprintf(buf, "%u\n", sleep_timeout / HZ);
658 }
659
660 static ssize_t sleep_timeout_store(struct kobject *kobj,
661 struct kobj_attribute *attr,
662 const char *buf, size_t n)
663 {
664 struct omap_uart_state *uart;
665 unsigned int value;
666
667 if (sscanf(buf, "%u", &value) != 1) {
668 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
669 return -EINVAL;
670 }
671 sleep_timeout = value * HZ;
672 list_for_each_entry(uart, &uart_list, node) {
673 uart->timeout = sleep_timeout;
674 if (uart->timeout)
675 mod_timer(&uart->timer, jiffies + uart->timeout);
676 else
677 /* A zero value means disable timeout feature */
678 _omap_uart_block_sleep(uart);
679 }
680 return n;
681 }
682
683 static struct kobj_attribute sleep_timeout_attr =
684 __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
685 #endif
686
687 #else
688 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
689 #endif /* CONFIG_PM */
690
691 static int fifo_idleblk_get(void *data, u64 *val)
692 {
693 *val = fifo_idleblks;
694 return 0;
695 }
696
697 static int fifo_idleblk_set(void *data, u64 val)
698 {
699 fifo_idleblks = 0;
700 return 0;
701 }
702
703 DEFINE_SIMPLE_ATTRIBUTE(fifo_idleblk_fops, fifo_idleblk_get, fifo_idleblk_set, "%llu\n");
704 void omap_serial_early_init(void)
705 {
706 }
707
708 void omap_serial_ctsrts_init(unsigned char ctsrts[])
709 {
710 #if defined(CONFIG_SERIAL_OMAP) && \
711 defined(CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL)
712 serial_platform_data[0].ctsrts = ctsrts[0];
713 serial_platform_data[1].ctsrts = ctsrts[1];
714 serial_platform_data[2].ctsrts = ctsrts[2];
715 #endif
716 }
717
718 void omap_uart_set_uart0_padconf(int padconf)
719 {
720 uart0_padconf = padconf;
721 }
722
723 void my_omap_serial_init(int wake_gpio_strobe,
724 unsigned int wake_strobe_enable_mask)
725 {
726 int i;
727 char name[16];
728
729 debugfs_create_file("fifo_idle_block_count", 0644, NULL, NULL, &fifo_idleblk_fops);
730 /*
731 * Make sure the serial ports are muxed on at this point.
732 * You have to mux them off in device drivers later on
733 * if not needed.
734 */
735
736 i=2;
737 {
738 struct plat_serialomap_port *p = serial_platform_data + i;
739 struct omap_uart_state *uart = &omap_uart[i];
740
741 if (wake_strobe_enable_mask & (1 << i))
742 p->wake_gpio_strobe = wake_gpio_strobe;
743
744 sprintf(name, "uart%d_ick", i+1);
745 uart->ick = clk_get(NULL, name);
746 if (IS_ERR(uart->ick)) {
747 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
748 uart->ick = NULL;
749 }
750
751 sprintf(name, "uart%d_fck", i+1);
752 uart->fck = clk_get(NULL, name);
753 if (IS_ERR(uart->fck)) {
754 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
755 uart->fck = NULL;
756 }
757
758 if (!uart->ick || !uart->fck)
759 return;
760
761 uart->num = i;
762 p->private_data = uart;
763 uart->p = p;
764 list_add(&uart->node, &uart_list);
765
766 omap_uart_enable_clocks(uart);
767 omap_uart_reset(uart);
768 omap_uart_rtspad_init(uart);
769 omap_uart_idle_init(uart);
770 }
771 }
772
773 int my_omap_hs_init(void)
774 {
775 int ret = 0;
776
777 ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices));
778 if (ret) {
779 printk(KERN_ERR "Error adding uart devices (%d)\n", ret);
780 return ret;
781 }
782 return ret;
783 }
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