--- /dev/null
+From f8a6bbe8437ae48f5638a58472e5bb8c3f9101cf Mon Sep 17 00:00:00 2001
+From: Saeed Bishara <saeed@marvell.com>
+Date: Sun, 14 Feb 2010 18:28:46 +0200
+Subject: [PATCH] arm: invalidate TLBs when enabling mmu
+
+
+Signed-off-by: Saeed Bishara <saeed@marvell.com>
+---
+ arch/arm/boot/compressed/head.S | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 40ef902..f421d06 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -481,6 +481,7 @@ __armv7_mmu_cache_on:
+ mcr p15, 0, r0, c1, c0, 0 @ load control register
+ mrc p15, 0, r0, c1, c0, 0 @ and read it back
+ mov r0, #0
++ mcr p15, 0, r0, c8, c7, 0 @ invalidate I,D TLBs
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+ mov pc, r12
+
+--
+1.6.0.4
+