obj-m += kexec_load.o headphone_cons.o
kexec_load-objs := kexec.o machine_kexec.o mmu.o sys.o core.o relocate_kernel.o \
proc-v7.o tlb-v7.o cache-v7.o abort-ev7.o pabort-v7.o copypage-v6.o driver_sys.o
+headphone_cons-objs := hs_cons.o omap2_serial.o
all:
PATH=$(CROSS_PATH):$(PATH) CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) make -C $(KDIR) M=$(PWD) modules
+++ /dev/null
-/*
- * Provide kernel console on headphone jack
- */
-
-#include <linux/module.h>
-#include <linux/gpio_mapping.h>
-#include <linux/gpio.h>
-
-static int hs_switch = -1;
-
-/*
- * int add_preferred_console(char *name, int idx, char *options)
- * c0069208 T add_preferred_console
- */
-
-static int (*add_preferred_console)(char *, int, char*) = (int (*)(char*, int, char*))0xc0069208;
-
-static int __init headphone_cons_init(void)
-{
- /* Get the headset switch gpio number from devtree */
- hs_switch = get_gpio_by_name("headset_uart_switch");
- if (hs_switch < 0)
- return -EINVAL;
-
- printk(KERN_INFO "headset_uart_switch: %d\n", hs_switch);
-
- printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
-
-#if 0
- /* configure headset switch gpio as output and
- direction based on devtree setting */
- if (gpio_request(hs_switch, "mapphone audio headset uart switch") < 0)
- return -ENODEV;
-#endif
-
- /* route kernel uart out headset jack */
- gpio_direction_output(hs_switch, 0);
- printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
-
- add_preferred_console("ttyS", 0, "115200");
- return 0;
-}
-
-static void __exit headphone_cons_exit(void)
-{
- if (hs_switch < 0)
- return;
-
- printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
- gpio_direction_output(hs_switch, 1);
- printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
-}
-
-
-module_init(headphone_cons_init);
-module_exit(headphone_cons_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Gernoth <michael@gernoth.net>");
--- /dev/null
+/*
+ * Provide kernel console on headphone jack
+ *
+ * Copyright (C) 2011 Michael Gernoth <michael@gernoth.net>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio_mapping.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/serial_reg.h>
+#include <linux/clk.h>
+
+#include <plat/board.h>
+#include <plat/control.h>
+#include <asm/mach/serial_omap.h>
+
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+static int hs_switch = -1;
+
+/*
+ * int add_preferred_console(char *name, int idx, char *options)
+ * c0069208 T add_preferred_console
+ */
+
+static int (*add_preferred_console)(char *, int, char*) = (int (*)(char*, int, char*))0xc0069208;
+
+void my_omap_serial_init(int wake_gpio_strobe, unsigned int wake_strobe_enable_mask);
+int my_omap_hs_init(void);
+
+#define MAPPHONE_BPWAKE_STROBE_GPIO 157
+
+static int __init headphone_cons_init(void)
+{
+ /* Get the headset switch gpio number from devtree */
+ hs_switch = get_gpio_by_name("headset_uart_switch");
+ if (hs_switch < 0)
+ return -EINVAL;
+
+ printk(KERN_INFO "headset_uart_switch: %d\n", hs_switch);
+
+ printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
+ if (!gpio_get_value(hs_switch))
+ return -ENODEV;
+
+ printk(KERN_INFO "Enabling UART3...\n");
+ my_omap_serial_init(MAPPHONE_BPWAKE_STROBE_GPIO, 0x01);
+ my_omap_hs_init();
+
+ /* route kernel uart out headset jack */
+ gpio_direction_output(hs_switch, 0);
+ printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
+
+ //add_preferred_console("ttyS", 2, "115200");
+ return 0;
+}
+
+#if 0
+static void __exit headphone_cons_exit(void)
+{
+ if (hs_switch < 0)
+ return;
+
+ printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
+ gpio_direction_output(hs_switch, 1);
+ printk(KERN_INFO "value: %d\n", gpio_get_value(hs_switch));
+}
+#endif
+
+
+module_init(headphone_cons_init);
+#if 0
+module_exit(headphone_cons_exit);
+#endif
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Michael Gernoth <michael@gernoth.net>");
--- /dev/null
+/*
+ * arch/arm/mach-omap2/serial.c
+ *
+ * OMAP2 serial support.
+ *
+ * Copyright (C) 2005-2008 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * Major rework for PM support by Kevin Hilman
+ *
+ * Based off of arch/arm/mach-omap/omap1/serial.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial_reg.h>
+#include <linux/clk.h>
+#ifdef CONFIG_SERIAL_OMAP
+#include <linux/platform_device.h>
+#endif
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/debugfs.h>
+
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/clock.h>
+#include <plat/control.h>
+#include <mach/gpio.h>
+#include <plat/omap-serial.h>
+
+#include <asm/mach/serial_omap.h>
+
+#include "prm.h"
+#include "pm.h"
+#include "prm-regbits-34xx.h"
+
+#define OMAP_CTRL_REGADDR(reg) (OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE) + (reg))
+
+void omap_ctrl_writew(u16 val, u16 offset)
+{
+ __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+}
+
+u16 omap_ctrl_readw(u16 offset)
+{
+ return __raw_readw(OMAP_CTRL_REGADDR(offset));
+}
+
+#define DEFAULT_TIMEOUT HZ
+
+struct omap_uart_state {
+ int num;
+ int can_sleep;
+ struct timer_list timer;
+ u32 timeout;
+
+ void __iomem *wk_st;
+ void __iomem *wk_en;
+ u32 wk_mask;
+ u32 padconf;
+
+ u32 rts_padconf;
+ int rts_override;
+ u16 rts_padvalue;
+
+ struct clk *ick;
+ struct clk *fck;
+ int clocked;
+
+ struct plat_serialomap_port *p;
+ struct list_head node;
+
+#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+ int context_valid;
+
+ /* Registers to be saved/restored for OFF-mode */
+ u16 dll;
+ u16 dlh;
+ u16 ier;
+ u16 sysc;
+ u16 scr;
+ u16 wer;
+#endif
+};
+
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
+static LIST_HEAD(uart_list);
+static unsigned int fifo_idleblks = 0;
+static int uart0_padconf = 0x180;
+
+static struct plat_serialomap_port serial_platform_data[] = {
+ {
+ .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART1_BASE),
+ .irq = 72,
+ .regshift = 2,
+#ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
+ .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
+#endif
+ .flags = UPF_BOOT_AUTOCONF,
+ },
+ {
+ .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART2_BASE),
+ .irq = 73,
+ .regshift = 2,
+#ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
+ .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
+#endif
+ .flags = UPF_BOOT_AUTOCONF,
+ },
+ {
+ .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART3_BASE),
+ .irq = 74,
+ .regshift = 2,
+#ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
+ .ctsrts = UART_EFR_RTS,
+#endif
+ .flags = UPF_BOOT_AUTOCONF,
+ },
+};
+
+#if 0
+static struct resource omap2_uart1_resources[] = {
+ {
+ .start = OMAP_UART1_BASE,
+ .end = OMAP_UART1_BASE + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 72,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource omap2_uart2_resources[] = {
+ {
+ .start = OMAP_UART2_BASE,
+ .end = OMAP_UART2_BASE + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 73,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+#endif
+
+static struct resource omap2_uart3_resources[] = {
+ {
+ .start = OMAP_UART3_BASE,
+ .end = OMAP_UART3_BASE + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 74,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+#ifdef CONFIG_MACH_OMAP_ZOOM2
+static struct resource omap2_quaduart_resources[] = {
+ {
+ .start = 0x10000000,
+ .end = 0x10000000 + (0x16 << 1),
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = OMAP_GPIO_IRQ(102),
+ .flags = IORESOURCE_IRQ,
+ }
+};
+#endif
+
+#if 0
+/* OMAP UART platform structure */
+static struct platform_device uart1_device = {
+ .name = "omap-uart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(omap2_uart1_resources),
+ .resource = omap2_uart1_resources,
+ .dev.platform_data = &serial_platform_data[0],
+};
+static struct platform_device uart2_device = {
+ .name = "omap-uart",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(omap2_uart2_resources),
+ .resource = omap2_uart2_resources,
+ .dev.platform_data = &serial_platform_data[1],
+};
+#endif
+static struct platform_device uart3_device = {
+ .name = "omap-uart",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(omap2_uart3_resources),
+ .resource = omap2_uart3_resources,
+ .dev.platform_data = &serial_platform_data[2],
+};
+
+static struct platform_device *uart_devices[] = {
+ &uart3_device,
+};
+
+static inline unsigned int serial_read_reg(struct plat_serialomap_port *up,
+ int offset)
+{
+ offset <<= up->regshift;
+ return (unsigned int)__raw_readb(up->membase + offset);
+}
+
+static inline void serial_write_reg(struct plat_serialomap_port *p, int offset,
+ int value)
+{
+ offset <<= p->regshift;
+ __raw_writeb(value, p->membase + offset);
+}
+
+/*
+ * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * properly. Note that the TX watermark initialization may not be needed
+ * once the 8250.c watermark handling code is merged.
+ */
+static inline void omap_uart_reset(struct omap_uart_state *uart)
+{
+ struct plat_serialomap_port *p = uart->p;
+
+ serial_write_reg(p, UART_OMAP_MDR1, 0x07);
+ serial_write_reg(p, UART_OMAP_SCR, 0x08);
+ serial_write_reg(p, UART_OMAP_MDR1, 0x00);
+ serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
+}
+
+static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
+{
+ if (uart->clocked)
+ return;
+
+ clk_enable(uart->ick);
+ clk_enable(uart->fck);
+ uart->clocked = 1;
+}
+
+#ifdef CONFIG_PM
+#ifdef CONFIG_ARCH_OMAP3
+
+static void omap_uart_save_context(struct omap_uart_state *uart)
+{
+ u16 lcr = 0;
+ struct plat_serialomap_port *p = uart->p;
+
+ if (!enable_off_mode)
+ return;
+
+ /* FIXME
+ * For omap3430 CORE/PERR OFF isn't temporarily supported,
+ * so no need to save&restore the context of serial.
+ */
+ if (cpu_is_omap34xx())
+ return;
+
+ lcr = serial_read_reg(p, UART_LCR);
+ serial_write_reg(p, UART_LCR, 0xBF);
+ uart->dll = serial_read_reg(p, UART_DLL);
+ uart->dlh = serial_read_reg(p, UART_DLM);
+ serial_write_reg(p, UART_LCR, lcr);
+ uart->ier = serial_read_reg(p, UART_IER);
+ uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
+ uart->scr = serial_read_reg(p, UART_OMAP_SCR);
+ uart->wer = serial_read_reg(p, UART_OMAP_WER);
+
+ uart->context_valid = 1;
+}
+
+static void omap_uart_restore_context(struct omap_uart_state *uart)
+{
+ u16 efr = 0;
+ struct plat_serialomap_port *p = uart->p;
+
+ if (!enable_off_mode)
+ return;
+
+ if (!uart->context_valid)
+ return;
+
+ /* FIXME
+ * For omap3430 CORE/PERR OFF isn't temporarily supported,
+ * so no need to save&restore the context of serial.
+ */
+ if (cpu_is_omap34xx())
+ return;
+
+ uart->context_valid = 0;
+
+ serial_write_reg(p, UART_OMAP_MDR1, 0x7);
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ efr = serial_read_reg(p, UART_EFR);
+ serial_write_reg(p, UART_EFR, UART_EFR_ECB);
+ serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+ serial_write_reg(p, UART_IER, 0x0);
+#ifdef CONFIG_SERIAL_OMAP
+ serial_write_reg(p, UART_FCR, fcr[uart->num]);
+#else
+ serial_write_reg(p, UART_FCR, 0xA1);
+#endif
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(p, UART_DLL, uart->dll);
+ serial_write_reg(p, UART_DLM, uart->dlh);
+ serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+ serial_write_reg(p, UART_IER, uart->ier);
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(p, UART_EFR, efr);
+ serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
+ serial_write_reg(p, UART_OMAP_SCR, uart->scr);
+ serial_write_reg(p, UART_OMAP_WER, uart->wer);
+ serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
+ serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+}
+#else
+static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
+static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
+#endif /* CONFIG_ARCH_OMAP3 */
+
+static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
+ int enable)
+{
+ struct plat_serialomap_port *p = uart->p;
+ u16 sysc;
+
+ sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
+ if (enable)
+ sysc |= 0x2 << 3;
+ else
+ sysc |= 0x1 << 3;
+
+ serial_write_reg(p, UART_OMAP_SYSC, sysc);
+}
+
+static inline void omap_uart_disable_rtspullup(struct omap_uart_state *uart)
+{
+ if (!uart->rts_padconf || !uart->rts_override)
+ return;
+ omap_ctrl_writew(uart->rts_padvalue, uart->rts_padconf);
+ uart->rts_override = 0;
+}
+
+static inline void omap_uart_enable_rtspullup(struct omap_uart_state *uart)
+{
+ if (!uart->rts_padconf || uart->rts_override)
+ return;
+
+ uart->rts_padvalue = omap_ctrl_readw(uart->rts_padconf);
+ omap_ctrl_writew(0x18 | 0x7, uart->rts_padconf);
+ uart->rts_override = 1;
+}
+
+static inline void omap_uart_restore(struct omap_uart_state *uart)
+{
+ omap_uart_enable_clocks(uart);
+ omap_uart_restore_context(uart);
+}
+
+static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
+{
+ if (!uart->clocked)
+ return;
+ omap_uart_save_context(uart);
+ uart->clocked = 0;
+ clk_disable(uart->ick);
+ clk_disable(uart->fck);
+}
+
+static void _omap_uart_block_sleep(struct omap_uart_state *uart)
+{
+ omap_uart_restore(uart);
+
+ omap_uart_smart_idle_enable(uart, 0);
+ uart->can_sleep = 0;
+ if (uart->timeout)
+ mod_timer(&uart->timer, jiffies + uart->timeout);
+ else
+ del_timer(&uart->timer);
+}
+
+#if 0
+static void omap_uart_block_sleep(int num)
+{
+ struct omap_uart_state *uart;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ if (num == uart->num)
+ _omap_uart_block_sleep(uart);
+ return;
+ }
+}
+EXPORT_SYMBOL(omap_uart_block_sleep);
+#endif
+
+static void omap_uart_allow_sleep(struct omap_uart_state *uart)
+{
+ if (!uart->clocked)
+ return;
+
+ omap_uart_smart_idle_enable(uart, 1);
+ uart->can_sleep = 1;
+ del_timer(&uart->timer);
+}
+
+static void omap_uart_idle_timer(unsigned long data)
+{
+ struct omap_uart_state *uart = (struct omap_uart_state *)data;
+
+ omap_uart_allow_sleep(uart);
+}
+
+void omap_uart_prepare_idle(int num)
+{
+ struct omap_uart_state *uart;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ if (num == uart->num && uart->can_sleep) {
+
+ omap_uart_enable_rtspullup(uart);
+ /*
+ * There seems to be a window here where
+ * data could still be on the way to the
+ * fifo. This delay is ~1 byte time @ 115.2k
+ */
+ if (uart->num == 0)
+ udelay(80);
+
+#ifdef CONFIG_SERIAL_OMAP
+ if (are_driveromap_uarts_active(num)) {
+ fifo_idleblks++;
+ _omap_uart_block_sleep(uart);
+ omap_uart_disable_rtspullup(uart);
+ return;
+ }
+#endif
+ omap_uart_disable_clocks(uart);
+ return;
+ }
+ }
+}
+
+void omap_uart_resume_idle(int num)
+{
+ struct omap_uart_state *uart;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ if (num == uart->num) {
+ omap_uart_restore(uart);
+ omap_uart_disable_rtspullup(uart);
+
+ /* Check for IO pad wakeup */
+ if (cpu_is_omap34xx() && uart->padconf) {
+ u16 p = omap_ctrl_readw(uart->padconf);
+
+ if (p & OMAP3_PADCONF_WAKEUPEVENT0)
+ _omap_uart_block_sleep(uart);
+ }
+
+ /* Check for normal UART wakeup */
+ if (__raw_readl(uart->wk_st) & uart->wk_mask) {
+ _omap_uart_block_sleep(uart);
+ }
+
+ return;
+ }
+ }
+}
+
+void omap_uart_prepare_suspend(void)
+{
+ struct omap_uart_state *uart;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ omap_uart_allow_sleep(uart);
+ }
+}
+
+int omap_uart_can_sleep(void)
+{
+ struct omap_uart_state *uart;
+ int can_sleep = 1;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ if (!uart->clocked)
+ continue;
+
+ if (!uart->can_sleep) {
+ can_sleep = 0;
+ continue;
+ }
+
+#ifdef CONFIG_SERIAL_OMAP
+ if (are_driveromap_uarts_active(uart->num)) {
+ can_sleep = 0;
+ continue;
+ }
+#endif
+
+ /* This UART can now safely sleep. */
+ omap_uart_allow_sleep(uart);
+ }
+
+ return can_sleep;
+}
+
+/**
+ * omap_uart_interrupt()
+ *
+ * This handler is used only to detect that *any* UART interrupt has
+ * occurred. It does _nothing_ to handle the interrupt. Rather,
+ * any UART interrupt will trigger the inactivity timer so the
+ * UART will not idle or sleep for its timeout period.
+ *
+ **/
+static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
+{
+ struct omap_uart_state *uart = dev_id;
+
+ _omap_uart_block_sleep(uart);
+
+ return IRQ_NONE;
+}
+
+static u32 sleep_timeout = DEFAULT_TIMEOUT;
+
+static void omap_uart_rtspad_init(struct omap_uart_state *uart)
+{
+ if (!cpu_is_omap34xx())
+ return;
+ switch(uart->num) {
+ case 0:
+ uart->rts_padconf = 0x17e;
+ break;
+ case 1:
+ uart->rts_padconf = 0x176;
+ break;
+ case 2:
+/* uart->rts_padconf = 0x19c; */
+ break;
+ default:
+ uart->rts_padconf = 0;
+ break;
+ }
+}
+
+static void omap_uart_idle_init(struct omap_uart_state *uart)
+{
+ u32 v;
+ struct plat_serialomap_port *p = uart->p;
+ int ret;
+
+ uart->can_sleep = 0;
+ uart->timeout = sleep_timeout;
+ if (!uart->timeout)
+ _omap_uart_block_sleep(uart);
+ else {
+ setup_timer(&uart->timer, omap_uart_idle_timer,
+ (unsigned long) uart);
+ mod_timer(&uart->timer, jiffies + uart->timeout);
+ omap_uart_smart_idle_enable(uart, 0);
+ }
+
+ if (cpu_is_omap34xx()) {
+ u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
+ u32 wk_mask = 0;
+ u32 padconf = 0;
+
+ uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
+ uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
+ switch (uart->num) {
+ case 0:
+ wk_mask = OMAP3430_ST_UART1_MASK;
+ padconf = uart0_padconf;
+ break;
+ case 1:
+ wk_mask = OMAP3430_ST_UART2_MASK;
+ padconf = 0x17a;
+ break;
+ case 2:
+ wk_mask = OMAP3430_ST_UART3_MASK;
+ padconf = 0x19e;
+ break;
+ }
+ uart->wk_mask = wk_mask;
+ uart->padconf = padconf;
+ } else if (cpu_is_omap24xx()) {
+ u32 wk_mask = 0;
+
+ if (cpu_is_omap2430()) {
+ uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
+ uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
+ } else if (cpu_is_omap2420()) {
+ uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
+ uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
+ }
+ switch (uart->num) {
+ case 0:
+ wk_mask = OMAP24XX_ST_UART1_MASK;
+ break;
+ case 1:
+ wk_mask = OMAP24XX_ST_UART2_MASK;
+ break;
+ case 2:
+ wk_mask = OMAP24XX_ST_UART3_MASK;
+ break;
+ }
+ uart->wk_mask = wk_mask;
+ } else {
+ uart->wk_en = 0;
+ uart->wk_st = 0;
+ uart->wk_mask = 0;
+ uart->padconf = 0;
+ }
+
+ /* Set wake-enable bit */
+ if (uart->wk_en && uart->wk_mask) {
+ v = __raw_readl(uart->wk_en);
+ v |= uart->wk_mask;
+ __raw_writel(v, uart->wk_en);
+ }
+
+ /* Ensure IOPAD wake-enables are set */
+ if (cpu_is_omap34xx() && uart->padconf) {
+ u16 v;
+
+ v = omap_ctrl_readw(uart->padconf);
+ v |= OMAP3_PADCONF_WAKEUPENABLE0;
+ omap_ctrl_writew(v, uart->padconf);
+ }
+
+ p->flags |= UPF_SHARE_IRQ;
+ ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
+ "serial idle", (void *)uart);
+ WARN_ON(ret);
+}
+
+void omap_uart_enable_irqs(int enable)
+{
+ int ret;
+ struct omap_uart_state *uart;
+
+ list_for_each_entry(uart, &uart_list, node) {
+ if (enable)
+ ret = request_irq(uart->p->irq, omap_uart_interrupt,
+ IRQF_SHARED, "serial idle", (void *)uart);
+ else
+ free_irq(uart->p->irq, (void *)uart);
+ }
+}
+
+#if 0
+static ssize_t sleep_timeout_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%u\n", sleep_timeout / HZ);
+}
+
+static ssize_t sleep_timeout_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ struct omap_uart_state *uart;
+ unsigned int value;
+
+ if (sscanf(buf, "%u", &value) != 1) {
+ printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
+ return -EINVAL;
+ }
+ sleep_timeout = value * HZ;
+ list_for_each_entry(uart, &uart_list, node) {
+ uart->timeout = sleep_timeout;
+ if (uart->timeout)
+ mod_timer(&uart->timer, jiffies + uart->timeout);
+ else
+ /* A zero value means disable timeout feature */
+ _omap_uart_block_sleep(uart);
+ }
+ return n;
+}
+
+static struct kobj_attribute sleep_timeout_attr =
+ __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#endif
+
+#else
+static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#endif /* CONFIG_PM */
+
+static int fifo_idleblk_get(void *data, u64 *val)
+{
+ *val = fifo_idleblks;
+ return 0;
+}
+
+static int fifo_idleblk_set(void *data, u64 val)
+{
+ fifo_idleblks = 0;
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fifo_idleblk_fops, fifo_idleblk_get, fifo_idleblk_set, "%llu\n");
+void omap_serial_early_init(void)
+{
+}
+
+void omap_serial_ctsrts_init(unsigned char ctsrts[])
+{
+#if defined(CONFIG_SERIAL_OMAP) && \
+ defined(CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL)
+ serial_platform_data[0].ctsrts = ctsrts[0];
+ serial_platform_data[1].ctsrts = ctsrts[1];
+ serial_platform_data[2].ctsrts = ctsrts[2];
+#endif
+}
+
+void omap_uart_set_uart0_padconf(int padconf)
+{
+ uart0_padconf = padconf;
+}
+
+void my_omap_serial_init(int wake_gpio_strobe,
+ unsigned int wake_strobe_enable_mask)
+{
+ int i;
+ char name[16];
+
+ debugfs_create_file("fifo_idle_block_count", 0644, NULL, NULL, &fifo_idleblk_fops);
+ /*
+ * Make sure the serial ports are muxed on at this point.
+ * You have to mux them off in device drivers later on
+ * if not needed.
+ */
+
+ i=2;
+ {
+ struct plat_serialomap_port *p = serial_platform_data + i;
+ struct omap_uart_state *uart = &omap_uart[i];
+
+ if (wake_strobe_enable_mask & (1 << i))
+ p->wake_gpio_strobe = wake_gpio_strobe;
+
+ sprintf(name, "uart%d_ick", i+1);
+ uart->ick = clk_get(NULL, name);
+ if (IS_ERR(uart->ick)) {
+ printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
+ uart->ick = NULL;
+ }
+
+ sprintf(name, "uart%d_fck", i+1);
+ uart->fck = clk_get(NULL, name);
+ if (IS_ERR(uart->fck)) {
+ printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
+ uart->fck = NULL;
+ }
+
+ if (!uart->ick || !uart->fck)
+ return;
+
+ uart->num = i;
+ p->private_data = uart;
+ uart->p = p;
+ list_add(&uart->node, &uart_list);
+
+ omap_uart_enable_clocks(uart);
+ omap_uart_reset(uart);
+ omap_uart_rtspad_init(uart);
+ omap_uart_idle_init(uart);
+ }
+}
+
+int my_omap_hs_init(void)
+{
+ int ret = 0;
+
+ ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices));
+ if (ret) {
+ printk(KERN_ERR "Error adding uart devices (%d)\n", ret);
+ return ret;
+ }
+ return ret;
+}
--- /dev/null
+/*
+ * OMAP2/3 Power Management Routines
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Jouni Hogander
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
+#define __ARCH_ARM_MACH_OMAP2_PM_H
+
+#include <plat/powerdomain.h>
+
+extern u32 enable_off_mode;
+extern u32 sleep_while_idle;
+extern u32 voltage_off_while_idle;
+extern unsigned int wakeup_timer_nseconds;
+extern u32 enable_abb_mode;
+
+extern void *omap3_secure_ram_storage;
+extern void omap3_pm_off_mode_enable(int);
+extern void omap_sram_idle(void);
+extern int omap3_can_sleep(void);
+extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+extern int omap3_idle_init(void);
+extern void vfp_pm_save_context(void);
+
+extern void lock_scratchpad_sem(void);
+extern void unlock_scratchpad_sem(void);
+
+struct prm_setup_vc {
+ u16 clksetup;
+ u16 voltsetup_time1;
+ u16 voltsetup_time2;
+ u16 voltoffset;
+ u16 voltsetup2;
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+ u16 vdd0_on;
+ u16 vdd0_onlp;
+ u16 vdd0_ret;
+ u16 vdd0_off;
+/* PRM_VC_CMD_VAL_1 specific bits */
+ u16 vdd1_on;
+ u16 vdd1_onlp;
+ u16 vdd1_ret;
+ u16 vdd1_off;
+
+/* Values for VDD registers */
+ u32 i2c_slave_ra;
+ u32 vdd_vol_ra;
+ u32 vdd_cmd_ra;
+ u32 vdd_ch_conf;
+ u32 vdd_i2c_cfg;
+};
+
+struct cpuidle_params {
+ u8 valid;
+ u32 sleep_latency;
+ u32 wake_latency;
+ u32 threshold;
+};
+
+extern void omap3_pm_init_vc(struct prm_setup_vc *setup_vc);
+#ifdef CONFIG_CPU_IDLE
+extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
+extern int omap3_bypass_cmd(u8 slave_addr, u8 reg_addr, u8 cmd);
+#else
+static inline void omap3_pm_init_cpuidle(
+ struct cpuidle_params *cpuidle_board_params)
+{
+}
+#endif
+
+extern int resource_set_opp_level(int res, u32 target_level, int flags);
+extern int resource_access_opp_lock(int res, int delta);
+#define resource_lock_opp(res) resource_access_opp_lock(res, 1)
+#define resource_unlock_opp(res) resource_access_opp_lock(res, -1)
+#define resource_get_opp_lock(res) resource_access_opp_lock(res, 0)
+
+#define OPP_IGNORE_LOCK 0x1
+#define OPP_IGNORE_NOTIFIER 0x2
+
+extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
+extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+
+extern u32 wakeup_timer_seconds;
+extern struct omap_dm_timer *gptimer_wakeup;
+
+#ifdef CONFIG_PM_DEBUG
+extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+extern int omap2_pm_debug;
+#else
+#define omap2_pm_dump(mode, resume, us) do {} while (0);
+#define omap2_pm_debug 0
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
+extern int pm_dbg_regset_save(int reg_set);
+extern int pm_dbg_regset_init(int reg_set);
+extern void pm_dbg_show_core_regs(void);
+extern void pm_dbg_show_wakeup_source(void);
+#else
+#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
+#define pm_dbg_regset_save(reg_set) do {} while (0);
+#define pm_dbg_regset_init(reg_set) do {} while (0);
+#define pm_dbg_show_core_regs() do {} while (0);
+#define pm_dbg_show_wakeup_source() do {} while (0);
+#endif /* CONFIG_PM_DEBUG */
+
+extern void omap24xx_idle_loop_suspend(void);
+
+extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
+ void __iomem *sdrc_power);
+extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
+extern void save_secure_ram_context(u32 *addr);
+extern void omap3_save_scratchpad_contents(void);
+
+extern unsigned int omap24xx_idle_loop_suspend_sz;
+extern unsigned int omap34xx_suspend_sz;
+extern unsigned int save_secure_ram_context_sz;
+extern unsigned int omap24xx_cpu_suspend_sz;
+extern unsigned int omap34xx_cpu_suspend_sz;
+
+#endif
--- /dev/null
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD 0x000
+#define MPU_MOD 0x100
+#define CORE_MOD 0x200
+#define GFX_MOD 0x300
+#define WKUP_MOD 0x400
+#define PLL_MOD 0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_GR_MOD OCP_MOD
+#define OMAP24XX_DSP_MOD 0x800
+
+#define OMAP2430_MDM_MOD 0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD -0x800
+#define OMAP3430ES2_SGX_MOD GFX_MOD
+#define OMAP3430_CCR_MOD PLL_MOD
+#define OMAP3430_DSS_MOD 0x600
+#define OMAP3430_CAM_MOD 0x700
+#define OMAP3430_PER_MOD 0x800
+#define OMAP3430_EMU_MOD 0x900
+#define OMAP3430_GR_MOD 0xa00
+#define OMAP3430_NEON_MOD 0xb00
+#define OMAP3430ES2_USBHOST_MOD 0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT 26
+#define OMAP2420_EN_MMC (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT 22
+#define OMAP24XX_EN_UART2 (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT 21
+#define OMAP24XX_EN_UART1 (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT 18
+#define OMAP24XX_EN_MCSPI2 (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT 17
+#define OMAP24XX_EN_MCSPI1 (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT 16
+#define OMAP24XX_EN_MCBSP2 (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT 15
+#define OMAP24XX_EN_MCBSP1 (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT 14
+#define OMAP24XX_EN_GPT12 (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT 13
+#define OMAP24XX_EN_GPT11 (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT 12
+#define OMAP24XX_EN_GPT10 (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT 11
+#define OMAP24XX_EN_GPT9 (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT 10
+#define OMAP24XX_EN_GPT8 (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT 9
+#define OMAP24XX_EN_GPT7 (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT 8
+#define OMAP24XX_EN_GPT6 (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT 7
+#define OMAP24XX_EN_GPT5 (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT 6
+#define OMAP24XX_EN_GPT4 (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT 5
+#define OMAP24XX_EN_GPT3 (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT 4
+#define OMAP24XX_EN_GPT2 (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT 3
+#define OMAP2420_EN_VLYNQ (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT 10
+#define OMAP2430_EN_GPIO5 (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT 9
+#define OMAP2430_EN_MCSPI3 (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT 8
+#define OMAP2430_EN_MMCHS2 (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT 7
+#define OMAP2430_EN_MMCHS1 (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT 2
+#define OMAP24XX_EN_UART3 (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT 0
+#define OMAP24XX_EN_USB (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT 11
+#define OMAP2430_EN_MDM_INTC (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT 6
+#define OMAP2430_EN_USBHS (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC_SHIFT 26
+#define OMAP2420_ST_MMC_MASK (1 << 26)
+#define OMAP24XX_ST_UART2_SHIFT 22
+#define OMAP24XX_ST_UART2_MASK (1 << 22)
+#define OMAP24XX_ST_UART1_SHIFT 21
+#define OMAP24XX_ST_UART1_MASK (1 << 21)
+#define OMAP24XX_ST_MCSPI2_SHIFT 18
+#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
+#define OMAP24XX_ST_MCSPI1_SHIFT 17
+#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
+#define OMAP24XX_ST_GPT12_SHIFT 14
+#define OMAP24XX_ST_GPT12_MASK (1 << 14)
+#define OMAP24XX_ST_GPT11_SHIFT 13
+#define OMAP24XX_ST_GPT11_MASK (1 << 13)
+#define OMAP24XX_ST_GPT10_SHIFT 12
+#define OMAP24XX_ST_GPT10_MASK (1 << 12)
+#define OMAP24XX_ST_GPT9_SHIFT 11
+#define OMAP24XX_ST_GPT9_MASK (1 << 11)
+#define OMAP24XX_ST_GPT8_SHIFT 10
+#define OMAP24XX_ST_GPT8_MASK (1 << 10)
+#define OMAP24XX_ST_GPT7_SHIFT 9
+#define OMAP24XX_ST_GPT7_MASK (1 << 9)
+#define OMAP24XX_ST_GPT6_SHIFT 8
+#define OMAP24XX_ST_GPT6_MASK (1 << 8)
+#define OMAP24XX_ST_GPT5_SHIFT 7
+#define OMAP24XX_ST_GPT5_MASK (1 << 7)
+#define OMAP24XX_ST_GPT4_SHIFT 6
+#define OMAP24XX_ST_GPT4_MASK (1 << 6)
+#define OMAP24XX_ST_GPT3_SHIFT 5
+#define OMAP24XX_ST_GPT3_MASK (1 << 5)
+#define OMAP24XX_ST_GPT2_SHIFT 4
+#define OMAP24XX_ST_GPT2_MASK (1 << 4)
+#define OMAP2420_ST_VLYNQ_SHIFT 3
+#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC_SHIFT 11
+#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
+#define OMAP2430_ST_GPIO5_SHIFT 10
+#define OMAP2430_ST_GPIO5_MASK (1 << 10)
+#define OMAP2430_ST_MCSPI3_SHIFT 9
+#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
+#define OMAP2430_ST_MMCHS2_SHIFT 8
+#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
+#define OMAP2430_ST_MMCHS1_SHIFT 7
+#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
+#define OMAP2430_ST_USBHS_SHIFT 6
+#define OMAP2430_ST_USBHS_MASK (1 << 6)
+#define OMAP24XX_ST_UART3_SHIFT 2
+#define OMAP24XX_ST_UART3_MASK (1 << 2)
+#define OMAP24XX_ST_USB_SHIFT 0
+#define OMAP24XX_ST_USB_MASK (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT 2
+#define OMAP24XX_EN_GPIOS (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT 0
+#define OMAP24XX_EN_GPT1 (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
+#define OMAP24XX_ST_GPIOS_MASK 2
+#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
+#define OMAP24XX_ST_GPT1_MASK 0
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM_SHIFT (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT 0
+#define OMAP3430_REV_MASK (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2 (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT 25
+#define OMAP3430_EN_MMC1 (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT 24
+#define OMAP3430_EN_MCSPI4 (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT 21
+#define OMAP3430_EN_MCSPI3 (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT 20
+#define OMAP3430_EN_MCSPI2 (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT 19
+#define OMAP3430_EN_MCSPI1 (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT 18
+#define OMAP3430_EN_I2C3 (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT 17
+#define OMAP3430_EN_I2C2 (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT 16
+#define OMAP3430_EN_I2C1 (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT 15
+#define OMAP3430_EN_UART2 (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT 14
+#define OMAP3430_EN_UART1 (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT 13
+#define OMAP3430_EN_GPT11 (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT 12
+#define OMAP3430_EN_GPT10 (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT 11
+#define OMAP3430_EN_MCBSP5 (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT 10
+#define OMAP3430_EN_MCBSP1 (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT 9
+#define OMAP3430_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430_EN_D2D (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT 3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT 4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2_SHIFT 25
+#define OMAP3430_ST_MMC2_MASK (1 << 25)
+#define OMAP3430_ST_MMC1_SHIFT 24
+#define OMAP3430_ST_MMC1_MASK (1 << 24)
+#define OMAP3430_ST_MCSPI4_SHIFT 21
+#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
+#define OMAP3430_ST_MCSPI3_SHIFT 20
+#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
+#define OMAP3430_ST_MCSPI2_SHIFT 19
+#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
+#define OMAP3430_ST_MCSPI1_SHIFT 18
+#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
+#define OMAP3430_ST_I2C3_SHIFT 17
+#define OMAP3430_ST_I2C3_MASK (1 << 17)
+#define OMAP3430_ST_I2C2_SHIFT 16
+#define OMAP3430_ST_I2C2_MASK (1 << 16)
+#define OMAP3430_ST_I2C1_SHIFT 15
+#define OMAP3430_ST_I2C1_MASK (1 << 15)
+#define OMAP3430_ST_UART2_SHIFT 14
+#define OMAP3430_ST_UART2_MASK (1 << 14)
+#define OMAP3430_ST_UART1_SHIFT 13
+#define OMAP3430_ST_UART1_MASK (1 << 13)
+#define OMAP3430_ST_GPT11_SHIFT 12
+#define OMAP3430_ST_GPT11_MASK (1 << 12)
+#define OMAP3430_ST_GPT10_SHIFT 11
+#define OMAP3430_ST_GPT10_MASK (1 << 11)
+#define OMAP3430_ST_MCBSP5_SHIFT 10
+#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
+#define OMAP3430_ST_MCBSP1_SHIFT 9
+#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
+#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
+#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
+#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
+#define OMAP3430_ST_D2D_SHIFT 3
+#define OMAP3430_ST_D2D_MASK (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1 (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT 3
+#define OMAP3430_EN_GPT12 (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT 1
+#define OMAP3430_EN_GPT1 (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT 0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT 7
+#define OMAP3430_EN_SR1 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT 6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12 (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT 1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2_SHIFT 7
+#define OMAP3430_ST_SR2_MASK (1 << 7)
+#define OMAP3430_ST_SR1_SHIFT 6
+#define OMAP3430_ST_SR1_MASK (1 << 6)
+#define OMAP3430_ST_GPIO1_SHIFT 3
+#define OMAP3430_ST_GPIO1_MASK (1 << 3)
+#define OMAP3430_ST_GPT12_SHIFT 1
+#define OMAP3430_ST_GPT12_MASK (1 << 1)
+#define OMAP3430_ST_GPT1_SHIFT 0
+#define OMAP3430_ST_GPT1_MASK (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT 1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6 (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT 17
+#define OMAP3430_EN_GPIO5 (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT 16
+#define OMAP3430_EN_GPIO4 (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT 15
+#define OMAP3430_EN_GPIO3 (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT 14
+#define OMAP3430_EN_GPIO2 (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT 13
+#define OMAP3430_EN_UART3 (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT 11
+#define OMAP3430_EN_GPT9 (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT 10
+#define OMAP3430_EN_GPT8 (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT 9
+#define OMAP3430_EN_GPT7 (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT 8
+#define OMAP3430_EN_GPT6 (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT 7
+#define OMAP3430_EN_GPT5 (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT 6
+#define OMAP3430_EN_GPT4 (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT 5
+#define OMAP3430_EN_GPT3 (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT 4
+#define OMAP3430_EN_GPT2 (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT 3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4 (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT 2
+#define OMAP3430_EN_MCBSP3 (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT 1
+#define OMAP3430_EN_MCBSP2 (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT 0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6_SHIFT 17
+#define OMAP3430_ST_GPIO6_MASK (1 << 17)
+#define OMAP3430_ST_GPIO5_SHIFT 16
+#define OMAP3430_ST_GPIO5_MASK (1 << 16)
+#define OMAP3430_ST_GPIO4_SHIFT 15
+#define OMAP3430_ST_GPIO4_MASK (1 << 15)
+#define OMAP3430_ST_GPIO3_SHIFT 14
+#define OMAP3430_ST_GPIO3_MASK (1 << 14)
+#define OMAP3430_ST_GPIO2_SHIFT 13
+#define OMAP3430_ST_GPIO2_MASK (1 << 13)
+#define OMAP3430_ST_UART3_SHIFT 11
+#define OMAP3430_ST_UART3_MASK (1 << 11)
+#define OMAP3430_ST_GPT9_SHIFT 10
+#define OMAP3430_ST_GPT9_MASK (1 << 10)
+#define OMAP3430_ST_GPT8_SHIFT 9
+#define OMAP3430_ST_GPT8_MASK (1 << 9)
+#define OMAP3430_ST_GPT7_SHIFT 8
+#define OMAP3430_ST_GPT7_MASK (1 << 8)
+#define OMAP3430_ST_GPT6_SHIFT 7
+#define OMAP3430_ST_GPT6_MASK (1 << 7)
+#define OMAP3430_ST_GPT5_SHIFT 6
+#define OMAP3430_ST_GPT5_MASK (1 << 6)
+#define OMAP3430_ST_GPT4_SHIFT 5
+#define OMAP3430_ST_GPT4_MASK (1 << 5)
+#define OMAP3430_ST_GPT3_SHIFT 4
+#define OMAP3430_ST_GPT3_MASK (1 << 4)
+#define OMAP3430_ST_GPT2_SHIFT 3
+#define OMAP3430_ST_GPT2_MASK (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE_SHIFT 0
+#define OMAP3430_EN_CORE_MASK (1 << 0)
+
+#endif
+
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT 24
+#define OMAP3430_ON_MASK (0xff << 24)
+#define OMAP3430_ONLP_SHIFT 16
+#define OMAP3430_ONLP_MASK (0xff << 16)
+#define OMAP3430_RET_SHIFT 8
+#define OMAP3430_RET_MASK (0xff << 8)
+#define OMAP3430_OFF_SHIFT 0
+#define OMAP3430_OFF_MASK (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT 24
+#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT 16
+#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT 8
+#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
+#define OMAP3430_TIMEOUTEN (1 << 3)
+#define OMAP3430_INITVDD (1 << 2)
+#define OMAP3430_FORCEUPDATE (1 << 1)
+#define OMAP3430_VPENABLE (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT 0
+#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT 0
+#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT 24
+#define OMAP3430_VDDMAX_MASK (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT 16
+#define OMAP3430_VDDMIN_MASK (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT 0
+#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT 0
+#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER_SHIFT 7
+#define OMAP3430_EN_PER_MASK (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3630_ABB_LDO_TRANXDONE_MASK (1 << 26)
+#define OMAP3630_ABB_LDO_TRANXDONE_ST (1 << 26)
+#define OMAP3430_WKUP_ST (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2 (1 << 25)
+#define OMAP3430_GRPSEL_MMC1 (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
+#define OMAP3430_GRPSEL_I2C3 (1 << 17)
+#define OMAP3430_GRPSEL_I2C2 (1 << 16)
+#define OMAP3430_GRPSEL_I2C1 (1 << 15)
+#define OMAP3430_GRPSEL_UART2 (1 << 14)
+#define OMAP3430_GRPSEL_UART1 (1 << 13)
+#define OMAP3430_GRPSEL_GPT11 (1 << 12)
+#define OMAP3430_GRPSEL_GPT10 (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
+#define OMAP3430_GRPSEL_D2D (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT 16
+#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEMRETSTATE (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6 (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5 (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4 (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3 (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2 (1 << 13)
+#define OMAP3430_GRPSEL_UART3 (1 << 11)
+#define OMAP3430_GRPSEL_GPT9 (1 << 10)
+#define OMAP3430_GRPSEL_GPT8 (1 << 9)
+#define OMAP3430_GRPSEL_GPT7 (1 << 8)
+#define OMAP3430_GRPSEL_GPT6 (1 << 7)
+#define OMAP3430_GRPSEL_GPT5 (1 << 6)
+#define OMAP3430_GRPSEL_GPT4 (1 << 5)
+#define OMAP3430_GRPSEL_GPT3 (1 << 4)
+#define OMAP3430_GRPSEL_GPT2 (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO (1 << 8)
+#define OMAP3430_GRPSEL_SR2 (1 << 7)
+#define OMAP3430_GRPSEL_SR1 (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1 (1 << 3)
+#define OMAP3430_GRPSEL_GPT12 (1 << 1)
+#define OMAP3430_GRPSEL_GPT1 (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2 (1 << 2)
+#define OMAP3430_RST2_IVA2 (1 << 1)
+#define OMAP3430_RST1_IVA2 (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST (1 << 11)
+#define OMAP3430_IVA2_SW_RST3 (1 << 10)
+#define OMAP3430_IVA2_SW_RST2 (1 << 9)
+#define OMAP3430_IVA2_SW_RST1 (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
+#define OMAP3430_FORCEWKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
+#define OMAP3430_FORCEWKUP_EN (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
+#define OMAP3430_VC_RAERR_ST (1 << 23)
+#define OMAP3430_VC_SAERR_ST (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
+#define OMAP3430_IO_ST (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
+#define OMAP3430_MPU_DPLL_ST (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_ST (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
+#define OMAP3430_CORE_DPLL_ST (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT 5
+#define OMAP3430_TRANSITION_ST (1 << 4)
+#define OMAP3430_EVGENOFF_ST (1 << 3)
+#define OMAP3430_EVGENON_ST (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3630_VC_BYPASS_ACK_EN (1 << 28)
+#define OMAP3630_VC_VP1_ACK_EN (1 << 27)
+#define OMAP3630_ABB_LDO_TRANXDONE_EN (1 << 26)
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
+#define OMAP3430_VC_RAERR_EN (1 << 23)
+#define OMAP3430_VC_SAERR_EN (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
+#define OMAP3430_IO_EN (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
+#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
+#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
+#define OMAP3430_TRANSITION_EN (1 << 4)
+#define OMAP3430_EVGENOFF_EN (1 << 3)
+#define OMAP3430_EVGENON_EN (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT 3
+#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT 1
+#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
+#define OMAP3430_ENABLE (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT 0
+#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT 0
+#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT 16
+#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT 6
+#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT 18
+#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT 16
+#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE (1 << 9)
+#define OMAP3430_MEM1RETSTATE (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT 6
+#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT 4
+#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO_CHAIN (1 << 16)
+#define OMAP3430_EN_IO (1 << 8)
+#define OMAP3430_EN_GPIO1 (1 << 3)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO_CHAIN (1 << 16)
+#define OMAP3430_ST_IO (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
+#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT 7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_SMPS_SA1_SHIFT 16
+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
+#define OMAP3430_SMPS_SA0_SHIFT 0
+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT 16
+#define OMAP3430_VOLRA1_MASK (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT 0
+#define OMAP3430_VOLRA0_MASK (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT 16
+#define OMAP3430_CMDRA1_MASK (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT 0
+#define OMAP3430_CMDRA0_MASK (0xff << 0)
+
+/* PRM_VC_CMD_VAL specific bits */
+#define OMAP3430_VC_CMD_ON_SHIFT 24
+#define OMAP3430_VC_CMD_ON_MASK (0xff << 24)
+#define OMAP3430_VC_CMD_ONLP_SHIFT 16
+#define OMAP3430_VC_CMD_ONLP_MASK (0xff << 16)
+#define OMAP3430_VC_CMD_RET_SHIFT 8
+#define OMAP3430_VC_CMD_RET_MASK (0xff << 8)
+#define OMAP3430_VC_CMD_OFF_SHIFT 0
+#define OMAP3430_VC_CMD_OFF_MASK (0xff << 0)
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1 (1 << 20)
+#define OMAP3430_RACEN1 (1 << 19)
+#define OMAP3430_RAC1 (1 << 18)
+#define OMAP3430_RAV1 (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
+#define OMAP3430_CMD0 (1 << 4)
+#define OMAP3430_RACEN0 (1 << 3)
+#define OMAP3430_RAC0 (1 << 2)
+#define OMAP3430_RAV0 (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER (1 << 5)
+#define OMAP3430_SREN (1 << 4)
+#define OMAP3430_HSEN (1 << 3)
+#define OMAP3430_MCODE_SHIFT 0
+#define OMAP3430_MCODE_MASK (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID (1 << 24)
+#define OMAP3430_DATA_SHIFT 16
+#define OMAP3430_DATA_MASK (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT 8
+#define OMAP3430_REGADDR_MASK (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT 0
+#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3 (1 << 2)
+#define OMAP3430_RST_GS (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT 8
+#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT 0
+#define OMAP3430_RSTTIME1_MASK (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST (1 << 10)
+#define OMAP3430_ICEPICK_RST (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
+#define OMAP3430_SECURE_WD_RST (1 << 5)
+#define OMAP3430_MPU_WD_RST (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE (1 << 4)
+#define OMAP3430_SEL_OFF (1 << 3)
+#define OMAP3430_AUTO_OFF (1 << 2)
+#define OMAP3430_AUTO_RET (1 << 1)
+#define OMAP3430_AUTO_SLEEP (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT 0
+#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT 6
+#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
+#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT 0
+#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT 16
+#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT 0
+#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT 0
+#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT 0
+#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL (1 << 3)
+#define OMAP3430_CLKOUT_POL (1 << 2)
+#define OMAP3430_CLKREQ_POL (1 << 1)
+#define OMAP3430_EXTVOL_POL (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
+#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* PRM_LDO_ABB_SETUP */
+#define OMAP3630_SR2_IN_TRANSITION (1 << 6)
+#define OMAP3630_SR2_STATUS_SHIFT 3
+#define OMAP3630_SR2_STATUS_MASK (0x3 << 3)
+#define OMAP3630_OPP_CHANGE (1 << 2)
+#define OMAP3630_OPP_SEL_SHIFT 0
+#define OMAP3630_OPP_SEL_MASK (0x3 << 0)
+
+/* PRM_LDO_ABB_CTRL */
+#define OMAP3630_SR2_WTCNT_VALUE_SHIFT 8
+#define OMAP3630_SR2_WTCNT_VALUE_MASK (0xff << 8)
+#define OMAP3630_SLEEP_RBB_SEL (1 << 3)
+#define OMAP3630_ACTIVE_FBB_SEL (1 << 2)
+#define OMAP3630_ACTIVE_RBB_SEL (1 << 1)
+#define OMAP3630_SR2EN (1 << 0)
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#define OMAP2420_PRM_REGADDR(module, reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+
+/*
+ * Architecture-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP2_PRCM_REVISION_OFFSET 0x0000
+#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
+#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
+#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
+#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
+#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
+#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
+#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
+#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
+#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
+#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP3_PRM_REVISION_OFFSET 0x0004
+#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
+#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
+#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
+#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
+#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
+#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
+#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
+#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
+#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
+#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
+#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET 0x0058
+#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
+#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
+#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
+#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
+#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
+#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
+#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
+#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
+#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
+#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
+#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/* 36xx register offsets in GR_MOD */
+#define OMAP3_PRM_LDO_ABB_SETUP_OFFSET 0X00f0
+#define OMAP3_PRM_LDO_ABB_CTRL_OFFSET 0x00f4
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL 0x0050
+#define RM_RSTTIME 0x0054
+#define RM_RSTST 0x0058
+
+#define PM_WKEN 0x00a0
+#define PM_WKEN1 PM_WKEN
+#define PM_WKST 0x00b0
+#define PM_WKST1 PM_WKST
+#define PM_WKDEP 0x00c8
+#define PM_EVGENCTRL 0x00d4
+#define PM_EVGENONTIM 0x00d8
+#define PM_EVGENOFFTIM 0x00dc
+#define PM_PWSTCTRL 0x00e0
+#define PM_PWSTST 0x00e4
+
+/* Omap2 specific registers */
+#define OMAP24XX_PM_WKEN2 0x00a4
+#define OMAP24XX_PM_WKST2 0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
+
+/* Omap3 specific registers */
+#define OMAP3430ES2_PM_WKEN3 0x00f0
+#define OMAP3430ES2_PM_WKST3 0x00b8
+
+#define OMAP3430_PM_MPUGRPSEL 0x00a4
+#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
+
+#define OMAP3430_PM_IVAGRPSEL 0x00a8
+#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
+
+#define OMAP3430_PM_PREPWSTST 0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
+
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+extern u32 prm_read_mod_reg(s16 module, u16 idx);
+extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+/* Read-modify-write bits in a PRM register (by domain) */
+static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+ return prm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+ return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT 0
+#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT 0
+#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT 0
+#define OMAP_SETUP_TIME_MASK (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT 6
+#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT 3
+#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT 0
+#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT 3
+#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT 1
+#define OMAP_ONLOADMODE_MASK (0x3 << 1)
+#define OMAP_ENABLE (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT 8
+#define OMAP_RSTTIME2_MASK (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT 0
+#define OMAP_RSTTIME1_MASK (0xff << 0)
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3 (1 << 2)
+#define OMAP_RST_GS (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ * PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION (1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ * PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT 0
+#define OMAP_POWERSTATEST_MASK (0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ * called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST (1 << 1)
+#define OMAP_GLOBALCOLD_RST (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ * PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP_SHIFT 4
+#define OMAP_EN_WKUP_MASK (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ * PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE (1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ * PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT 0
+#define OMAP_POWERSTATE_MASK (0x3 << 0)
+
+
+#endif
projects / ms2-kexec / commitdiff