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[proxmark3-svn] / armsrc / fpgaloader.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// Jonathan Westhues, April 2006
62638f87 3// iZsh <izsh at fail0verflow.com>, 2014
bd20f8f4 4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
15c4dc5a 9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
15c4dc5a 11//-----------------------------------------------------------------------------
f38a1528 12
9783989b 13#include <stdint.h>
14#include <stddef.h>
15#include <stdbool.h>
16#include "fpgaloader.h"
17#include "proxmark3.h"
f7e3ed82 18#include "util.h"
9ab7a6c7 19#include "string.h"
9783989b 20#include "BigBuf.h"
21#include "zlib.h"
22
23extern void Dbprintf(const char *fmt, ...);
24
25// remember which version of the bitstream we have already downloaded to the FPGA
26static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
27
28// this is where the bitstreams are located in memory:
29extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
30
31static uint8_t *fpga_image_ptr = NULL;
32static uint32_t uncompressed_bytes_cnt;
33
34static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
35#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
36#define OUTPUT_BUFFER_LEN 80
37#define FPGA_INTERLEAVE_SIZE 288
15c4dc5a 38
39//-----------------------------------------------------------------------------
40// Set up the Serial Peripheral Interface as master
41// Used to write the FPGA config word
42// May also be used to write to other SPI attached devices like an LCD
43//-----------------------------------------------------------------------------
44void SetupSpi(int mode)
45{
46 // PA10 -> SPI_NCS2 chip select (LCD)
47 // PA11 -> SPI_NCS0 chip select (FPGA)
48 // PA12 -> SPI_MISO Master-In Slave-Out
49 // PA13 -> SPI_MOSI Master-Out Slave-In
50 // PA14 -> SPI_SPCK Serial Clock
51
52 // Disable PIO control of the following pins, allows use by the SPI peripheral
53 AT91C_BASE_PIOA->PIO_PDR =
54 GPIO_NCS0 |
55 GPIO_NCS2 |
56 GPIO_MISO |
57 GPIO_MOSI |
58 GPIO_SPCK;
59
60 AT91C_BASE_PIOA->PIO_ASR =
61 GPIO_NCS0 |
62 GPIO_MISO |
63 GPIO_MOSI |
64 GPIO_SPCK;
65
66 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
67
68 //enable the SPI Peripheral clock
69 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
70 // Enable SPI
71 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
72
73 switch (mode) {
74 case SPI_FPGA_MODE:
75 AT91C_BASE_SPI->SPI_MR =
76 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
77 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
78 ( 0 << 7) | // Local Loopback Disabled
79 ( 1 << 4) | // Mode Fault Detection disabled
80 ( 0 << 2) | // Chip selects connected directly to peripheral
81 ( 0 << 1) | // Fixed Peripheral Select
82 ( 1 << 0); // Master Mode
83 AT91C_BASE_SPI->SPI_CSR[0] =
84 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
85 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
86 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
87 ( 8 << 4) | // Bits per Transfer (16 bits)
88 ( 0 << 3) | // Chip Select inactive after transfer
89 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
90 ( 0 << 0); // Clock Polarity inactive state is logic 0
91 break;
92 case SPI_LCD_MODE:
93 AT91C_BASE_SPI->SPI_MR =
94 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
95 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
96 ( 0 << 7) | // Local Loopback Disabled
97 ( 1 << 4) | // Mode Fault Detection disabled
98 ( 0 << 2) | // Chip selects connected directly to peripheral
99 ( 0 << 1) | // Fixed Peripheral Select
100 ( 1 << 0); // Master Mode
101 AT91C_BASE_SPI->SPI_CSR[2] =
102 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
103 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
104 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
105 ( 1 << 4) | // Bits per Transfer (9 bits)
106 ( 0 << 3) | // Chip Select inactive after transfer
107 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
108 ( 0 << 0); // Clock Polarity inactive state is logic 0
109 break;
110 default: // Disable SPI
111 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
112 break;
113 }
114}
115
116//-----------------------------------------------------------------------------
117// Set up the synchronous serial port, with the one set of options that we
118// always use when we are talking to the FPGA. Both RX and TX are enabled.
119//-----------------------------------------------------------------------------
120void FpgaSetupSsc(void)
121{
122 // First configure the GPIOs, and get ourselves a clock.
123 AT91C_BASE_PIOA->PIO_ASR =
124 GPIO_SSC_FRAME |
125 GPIO_SSC_DIN |
126 GPIO_SSC_DOUT |
127 GPIO_SSC_CLK;
128 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
129
130 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
131
132 // Now set up the SSC proper, starting from a known state.
133 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
134
135 // RX clock comes from TX clock, RX starts when TX starts, data changes
136 // on RX clock rising edge, sampled on falling edge
137 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
138
139 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
d714d3ef 140 // pulse, no output sync
902cb3c0 141 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
15c4dc5a 142
143 // clock comes from TK pin, no clock output, outputs change on falling
d714d3ef 144 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
902cb3c0 145 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
15c4dc5a 146
147 // tx framing is the same as the rx framing
148 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
149
150 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
151}
152
153//-----------------------------------------------------------------------------
154// Set up DMA to receive samples from the FPGA. We will use the PDC, with
155// a single buffer as a circular buffer (so that we just chain back to
156// ourselves, not to another buffer). The stuff to manipulate those buffers
157// is in apps.h, because it should be inlined, for speed.
158//-----------------------------------------------------------------------------
d19929cb 159bool FpgaSetupSscDma(uint8_t *buf, int len)
15c4dc5a 160{
4a71da5a 161 if (buf == NULL)
d19929cb 162 return false;
d19929cb 163
7bc95e2e 164 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
165 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
166 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
167 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
168 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
169 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
d19929cb 170
171 return true;
15c4dc5a 172}
173
9783989b 174
175//----------------------------------------------------------------------------
176// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
177// each call.
178//----------------------------------------------------------------------------
179static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
180{
181 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
182 compressed_fpga_stream->next_out = output_buffer;
183 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
184 fpga_image_ptr = output_buffer;
185 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
4a71da5a 186
187 if (res != Z_OK)
9783989b 188 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
4a71da5a 189
190 if (res < 0)
9783989b 191 return res;
9783989b 192 }
193
4a71da5a 194 ++uncompressed_bytes_cnt;
9783989b 195
196 return *fpga_image_ptr++;
197}
198
199//----------------------------------------------------------------------------
200// Undo the interleaving of several FPGA config files. FPGA config files
201// are combined into one big file:
202// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
203//----------------------------------------------------------------------------
204static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
205{
206 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
207 // skip undesired data belonging to other bitstream_versions
208 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
209 }
210
4a71da5a 211 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
9783989b 212}
213
214
215static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
216{
217 return BigBuf_malloc(items*size);
218}
219
220
221static void fpga_inflate_free(voidpf opaque, voidpf address)
222{
223 BigBuf_free();
224}
225
226
227//----------------------------------------------------------------------------
228// Initialize decompression of the respective (HF or LF) FPGA stream
229//----------------------------------------------------------------------------
230static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
231{
232 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
233
234 uncompressed_bytes_cnt = 0;
235
236 // initialize z_stream structure for inflate:
237 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
238 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
239 compressed_fpga_stream->next_out = output_buffer;
240 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
241 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
242 compressed_fpga_stream->zfree = &fpga_inflate_free;
243
244 inflateInit2(compressed_fpga_stream, 0);
245
246 fpga_image_ptr = output_buffer;
247
4a71da5a 248 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
9783989b 249 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
9783989b 250
251 // Check for a valid .bit file (starts with _bitparse_fixed_header)
4a71da5a 252 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
9783989b 253 return true;
4a71da5a 254
255 return false;
9783989b 256}
257
258
15c4dc5a 259static void DownloadFPGA_byte(unsigned char w)
260{
261#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
262 SEND_BIT(7);
263 SEND_BIT(6);
264 SEND_BIT(5);
265 SEND_BIT(4);
266 SEND_BIT(3);
267 SEND_BIT(2);
268 SEND_BIT(1);
269 SEND_BIT(0);
270}
271
9783989b 272// Download the fpga image starting at current stream position with length FpgaImageLen bytes
273static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 274{
275 int i=0;
276
277 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
278 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
279 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
280
281 SpinDelay(50);
282
283 LED_D_ON();
284
285 // These pins are inputs
286 AT91C_BASE_PIOA->PIO_ODR =
287 GPIO_FPGA_NINIT |
288 GPIO_FPGA_DONE;
289 // PIO controls the following pins
290 AT91C_BASE_PIOA->PIO_PER =
291 GPIO_FPGA_NINIT |
292 GPIO_FPGA_DONE;
293 // Enable pull-ups
294 AT91C_BASE_PIOA->PIO_PPUER =
295 GPIO_FPGA_NINIT |
296 GPIO_FPGA_DONE;
297
298 // setup initial logic state
299 HIGH(GPIO_FPGA_NPROGRAM);
300 LOW(GPIO_FPGA_CCLK);
301 LOW(GPIO_FPGA_DIN);
302 // These pins are outputs
303 AT91C_BASE_PIOA->PIO_OER =
304 GPIO_FPGA_NPROGRAM |
305 GPIO_FPGA_CCLK |
306 GPIO_FPGA_DIN;
307
308 // enter FPGA configuration mode
309 LOW(GPIO_FPGA_NPROGRAM);
310 SpinDelay(50);
311 HIGH(GPIO_FPGA_NPROGRAM);
312
313 i=100000;
314 // wait for FPGA ready to accept data signal
315 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
316 i--;
317 }
318
319 // crude error indicator, leave both red LEDs on and return
320 if (i==0){
321 LED_C_ON();
322 LED_D_ON();
323 return;
324 }
325
9783989b 326 for(i = 0; i < FpgaImageLen; i++) {
327 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
328 if (b < 0) {
329 Dbprintf("Error %d during FpgaDownload", b);
330 break;
15c4dc5a 331 }
9783989b 332 DownloadFPGA_byte(b);
15c4dc5a 333 }
9783989b 334
15c4dc5a 335 // continue to clock FPGA until ready signal goes high
336 i=100000;
337 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
338 HIGH(GPIO_FPGA_CCLK);
339 LOW(GPIO_FPGA_CCLK);
340 }
341 // crude error indicator, leave both red LEDs on and return
342 if (i==0){
343 LED_C_ON();
344 LED_D_ON();
345 return;
346 }
347 LED_D_OFF();
348}
349
9783989b 350
15c4dc5a 351/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
352 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
353 * After that the format is 1 byte section type (ASCII character), 2 byte length
354 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
355 * length.
356 */
9783989b 357static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 358{
15c4dc5a 359 int result = 0;
9783989b 360 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
361 uint16_t numbytes = 0;
362 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
363 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
364 numbytes++;
15c4dc5a 365 unsigned int current_length = 0;
366 if(current_name < 'a' || current_name > 'e') {
367 /* Strange section name, abort */
368 break;
369 }
370 current_length = 0;
371 switch(current_name) {
372 case 'e':
373 /* Four byte length field */
9783989b 374 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
375 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
376 numbytes += 2;
15c4dc5a 377 default: /* Fall through, two byte length field */
9783989b 378 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
379 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
380 numbytes += 2;
15c4dc5a 381 }
e30c654b 382
15c4dc5a 383 if(current_name != 'e' && current_length > 255) {
384 /* Maybe a parse error */
385 break;
386 }
e30c654b 387
15c4dc5a 388 if(current_name == section_name) {
389 /* Found it */
15c4dc5a 390 *section_length = current_length;
391 result = 1;
392 break;
393 }
e30c654b 394
9783989b 395 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
396 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
397 numbytes++;
398 }
15c4dc5a 399 }
e30c654b 400
15c4dc5a 401 return result;
402}
403
9783989b 404
405//----------------------------------------------------------------------------
406// Check which FPGA image is currently loaded (if any). If necessary
407// decompress and load the correct (HF or LF) image to the FPGA
408//----------------------------------------------------------------------------
7cc204bf 409void FpgaDownloadAndGo(int bitstream_version)
15c4dc5a 410{
9783989b 411 z_stream compressed_fpga_stream;
4a71da5a 412 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
9783989b 413
7cc204bf 414 // check whether or not the bitstream is already loaded
9783989b 415 if (downloaded_bitstream == bitstream_version)
7cc204bf 416 return;
417
9783989b 418 // make sure that we have enough memory to decompress
419 BigBuf_free();
420
421 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
7cc204bf 422 return;
15c4dc5a 423 }
e30c654b 424
9783989b 425 unsigned int bitstream_length;
426 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
427 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
428 downloaded_bitstream = bitstream_version;
429 }
15c4dc5a 430
9783989b 431 inflateEnd(&compressed_fpga_stream);
99cf19d9 432
433 BigBuf_free();
9783989b 434}
7cc204bf 435
9783989b 436
437//-----------------------------------------------------------------------------
438// Gather version information from FPGA image. Needs to decompress the begin
439// of the respective (HF or LF) image.
440// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
441// advisable to call this only once and store the results for later use.
442//-----------------------------------------------------------------------------
443void FpgaGatherVersion(int bitstream_version, char *dst, int len)
15c4dc5a 444{
15c4dc5a 445 unsigned int fpga_info_len;
4a71da5a 446 char tempstr[40] = {0x00};
9783989b 447 z_stream compressed_fpga_stream;
4a71da5a 448 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
9783989b 449
450 dst[0] = '\0';
451
452 // ensure that we can allocate enough memory for decompression:
453 BigBuf_free();
454
4a71da5a 455 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
9783989b 456 return;
9783989b 457
458 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
459 for (uint16_t i = 0; i < fpga_info_len; i++) {
460 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
461 if (i < sizeof(tempstr)) {
462 tempstr[i] = c;
463 }
15c4dc5a 464 }
9783989b 465 if (!memcmp("fpga_lf", tempstr, 7))
466 strncat(dst, "LF ", len-1);
467 else if (!memcmp("fpga_hf", tempstr, 7))
468 strncat(dst, "HF ", len-1);
469 }
470 strncat(dst, "FPGA image built", len-1);
471 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
472 strncat(dst, " for ", len-1);
473 for (uint16_t i = 0; i < fpga_info_len; i++) {
474 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
475 if (i < sizeof(tempstr)) {
476 tempstr[i] = c;
477 }
15c4dc5a 478 }
9783989b 479 strncat(dst, tempstr, len-1);
480 }
481 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
482 strncat(dst, " on ", len-1);
483 for (uint16_t i = 0; i < fpga_info_len; i++) {
484 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
485 if (i < sizeof(tempstr)) {
486 tempstr[i] = c;
487 }
15c4dc5a 488 }
9783989b 489 strncat(dst, tempstr, len-1);
490 }
491 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
492 strncat(dst, " at ", len-1);
493 for (uint16_t i = 0; i < fpga_info_len; i++) {
494 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
495 if (i < sizeof(tempstr)) {
496 tempstr[i] = c;
497 }
15c4dc5a 498 }
9783989b 499 strncat(dst, tempstr, len-1);
15c4dc5a 500 }
9783989b 501
502 strncat(dst, "\n", len-1);
503
504 inflateEnd(&compressed_fpga_stream);
15c4dc5a 505}
506
9783989b 507
15c4dc5a 508//-----------------------------------------------------------------------------
509// Send a 16 bit command/data pair to the FPGA.
510// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
511// where C is the 4 bit command and D is the 12 bit data
512//-----------------------------------------------------------------------------
f7e3ed82 513void FpgaSendCommand(uint16_t cmd, uint16_t v)
15c4dc5a 514{
515 SetupSpi(SPI_FPGA_MODE);
516 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
517 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
518}
519//-----------------------------------------------------------------------------
520// Write the FPGA setup word (that determines what mode the logic is in, read
521// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
522// avoid changing this function's occurence everywhere in the source code.
523//-----------------------------------------------------------------------------
f7e3ed82 524void FpgaWriteConfWord(uint8_t v)
15c4dc5a 525{
526 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
527}
528
529//-----------------------------------------------------------------------------
530// Set up the CMOS switches that mux the ADC: four switches, independently
531// closable, but should only close one at a time. Not an FPGA thing, but
532// the samples from the ADC always flow through the FPGA.
533//-----------------------------------------------------------------------------
f7e3ed82 534void SetAdcMuxFor(uint32_t whichGpio)
15c4dc5a 535{
536 AT91C_BASE_PIOA->PIO_OER =
537 GPIO_MUXSEL_HIPKD |
538 GPIO_MUXSEL_LOPKD |
539 GPIO_MUXSEL_LORAW |
540 GPIO_MUXSEL_HIRAW;
541
542 AT91C_BASE_PIOA->PIO_PER =
543 GPIO_MUXSEL_HIPKD |
544 GPIO_MUXSEL_LOPKD |
545 GPIO_MUXSEL_LORAW |
546 GPIO_MUXSEL_HIRAW;
547
548 LOW(GPIO_MUXSEL_HIPKD);
549 LOW(GPIO_MUXSEL_HIRAW);
550 LOW(GPIO_MUXSEL_LORAW);
551 LOW(GPIO_MUXSEL_LOPKD);
552
553 HIGH(whichGpio);
554}
7838f4be 555
556void Fpga_print_status(void)
557{
558 Dbprintf("Fgpa");
559 if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf(" mode.............HF");
560 else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf(" mode.............LF");
561 else Dbprintf(" mode.............%d", downloaded_bitstream);
562}
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