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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// Jonathan Westhues, April 2006
62638f87 3// iZsh <izsh at fail0verflow.com>, 2014
bd20f8f4 4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
15c4dc5a 9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
15c4dc5a 11//-----------------------------------------------------------------------------
9783989b 12#include "fpgaloader.h"
9783989b 13
14extern void Dbprintf(const char *fmt, ...);
15
16// remember which version of the bitstream we have already downloaded to the FPGA
17static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
18
19// this is where the bitstreams are located in memory:
20extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
21
22static uint8_t *fpga_image_ptr = NULL;
23static uint32_t uncompressed_bytes_cnt;
24
25static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
26#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
27#define OUTPUT_BUFFER_LEN 80
28#define FPGA_INTERLEAVE_SIZE 288
15c4dc5a 29
30//-----------------------------------------------------------------------------
31// Set up the Serial Peripheral Interface as master
32// Used to write the FPGA config word
33// May also be used to write to other SPI attached devices like an LCD
34//-----------------------------------------------------------------------------
35void SetupSpi(int mode)
36{
37 // PA10 -> SPI_NCS2 chip select (LCD)
38 // PA11 -> SPI_NCS0 chip select (FPGA)
39 // PA12 -> SPI_MISO Master-In Slave-Out
40 // PA13 -> SPI_MOSI Master-Out Slave-In
41 // PA14 -> SPI_SPCK Serial Clock
42
43 // Disable PIO control of the following pins, allows use by the SPI peripheral
44 AT91C_BASE_PIOA->PIO_PDR =
45 GPIO_NCS0 |
46 GPIO_NCS2 |
47 GPIO_MISO |
48 GPIO_MOSI |
49 GPIO_SPCK;
50
51 AT91C_BASE_PIOA->PIO_ASR =
52 GPIO_NCS0 |
53 GPIO_MISO |
54 GPIO_MOSI |
55 GPIO_SPCK;
56
57 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
58
59 //enable the SPI Peripheral clock
60 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
61 // Enable SPI
62 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
63
64 switch (mode) {
65 case SPI_FPGA_MODE:
66 AT91C_BASE_SPI->SPI_MR =
67 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
68 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
69 ( 0 << 7) | // Local Loopback Disabled
70 ( 1 << 4) | // Mode Fault Detection disabled
71 ( 0 << 2) | // Chip selects connected directly to peripheral
72 ( 0 << 1) | // Fixed Peripheral Select
73 ( 1 << 0); // Master Mode
74 AT91C_BASE_SPI->SPI_CSR[0] =
75 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
76 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
77 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
78 ( 8 << 4) | // Bits per Transfer (16 bits)
79 ( 0 << 3) | // Chip Select inactive after transfer
80 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
81 ( 0 << 0); // Clock Polarity inactive state is logic 0
82 break;
83 case SPI_LCD_MODE:
84 AT91C_BASE_SPI->SPI_MR =
85 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
86 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
87 ( 0 << 7) | // Local Loopback Disabled
88 ( 1 << 4) | // Mode Fault Detection disabled
89 ( 0 << 2) | // Chip selects connected directly to peripheral
90 ( 0 << 1) | // Fixed Peripheral Select
91 ( 1 << 0); // Master Mode
92 AT91C_BASE_SPI->SPI_CSR[2] =
93 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
94 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
95 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
96 ( 1 << 4) | // Bits per Transfer (9 bits)
97 ( 0 << 3) | // Chip Select inactive after transfer
98 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
99 ( 0 << 0); // Clock Polarity inactive state is logic 0
100 break;
101 default: // Disable SPI
102 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
103 break;
104 }
105}
106
107//-----------------------------------------------------------------------------
108// Set up the synchronous serial port, with the one set of options that we
109// always use when we are talking to the FPGA. Both RX and TX are enabled.
110//-----------------------------------------------------------------------------
f0a96745 111void FpgaSetupSscExt(uint8_t clearPCER) {
15c4dc5a 112 // First configure the GPIOs, and get ourselves a clock.
113 AT91C_BASE_PIOA->PIO_ASR =
114 GPIO_SSC_FRAME |
115 GPIO_SSC_DIN |
116 GPIO_SSC_DOUT |
117 GPIO_SSC_CLK;
118 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
119
f0a96745 120 if ( clearPCER )
121 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
122 else
123 AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_SSC);
15c4dc5a 124
125 // Now set up the SSC proper, starting from a known state.
126 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
127
128 // RX clock comes from TX clock, RX starts when TX starts, data changes
129 // on RX clock rising edge, sampled on falling edge
130 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
131
132 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
d714d3ef 133 // pulse, no output sync
902cb3c0 134 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
15c4dc5a 135
136 // clock comes from TK pin, no clock output, outputs change on falling
d714d3ef 137 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
902cb3c0 138 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
15c4dc5a 139
140 // tx framing is the same as the rx framing
141 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
142
143 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
144}
f0a96745 145void FpgaSetupSsc(void) {
146 FpgaSetupSscExt(TRUE);
147}
15c4dc5a 148//-----------------------------------------------------------------------------
149// Set up DMA to receive samples from the FPGA. We will use the PDC, with
150// a single buffer as a circular buffer (so that we just chain back to
151// ourselves, not to another buffer). The stuff to manipulate those buffers
152// is in apps.h, because it should be inlined, for speed.
153//-----------------------------------------------------------------------------
5bb62283 154bool FpgaSetupSscDma(uint8_t *buf, int len) {
155 if (buf == NULL) return false;
156
7bc95e2e 157 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
158 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
159 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
160 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
161 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
5bb62283 162 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
d19929cb 163 return true;
15c4dc5a 164}
165
9783989b 166
167//----------------------------------------------------------------------------
168// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
169// each call.
170//----------------------------------------------------------------------------
171static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
172{
173 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
174 compressed_fpga_stream->next_out = output_buffer;
175 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
176 fpga_image_ptr = output_buffer;
177 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
4a71da5a 178
179 if (res != Z_OK)
9783989b 180 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
4a71da5a 181
182 if (res < 0)
9783989b 183 return res;
9783989b 184 }
185
4a71da5a 186 ++uncompressed_bytes_cnt;
9783989b 187
188 return *fpga_image_ptr++;
189}
190
191//----------------------------------------------------------------------------
192// Undo the interleaving of several FPGA config files. FPGA config files
193// are combined into one big file:
194// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
195//----------------------------------------------------------------------------
196static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
197{
198 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
199 // skip undesired data belonging to other bitstream_versions
200 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
201 }
202
4a71da5a 203 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
9783989b 204}
205
206
207static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
208{
209 return BigBuf_malloc(items*size);
210}
211
212
213static void fpga_inflate_free(voidpf opaque, voidpf address)
214{
aaa1a9a2 215 // free eventually allocated BigBuf memory
216 BigBuf_free(); BigBuf_Clear_ext(false);
9783989b 217}
218
219
220//----------------------------------------------------------------------------
221// Initialize decompression of the respective (HF or LF) FPGA stream
222//----------------------------------------------------------------------------
223static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
224{
225 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
226
227 uncompressed_bytes_cnt = 0;
228
229 // initialize z_stream structure for inflate:
230 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
231 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
232 compressed_fpga_stream->next_out = output_buffer;
233 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
234 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
235 compressed_fpga_stream->zfree = &fpga_inflate_free;
236
237 inflateInit2(compressed_fpga_stream, 0);
238
239 fpga_image_ptr = output_buffer;
240
4a71da5a 241 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
9783989b 242 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
9783989b 243
244 // Check for a valid .bit file (starts with _bitparse_fixed_header)
4a71da5a 245 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
9783989b 246 return true;
4a71da5a 247
248 return false;
9783989b 249}
250
251
15c4dc5a 252static void DownloadFPGA_byte(unsigned char w)
253{
254#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
255 SEND_BIT(7);
256 SEND_BIT(6);
257 SEND_BIT(5);
258 SEND_BIT(4);
259 SEND_BIT(3);
260 SEND_BIT(2);
261 SEND_BIT(1);
262 SEND_BIT(0);
263}
264
9783989b 265// Download the fpga image starting at current stream position with length FpgaImageLen bytes
266static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 267{
268 int i=0;
269
270 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
271 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
272 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
273
274 SpinDelay(50);
275
276 LED_D_ON();
277
278 // These pins are inputs
279 AT91C_BASE_PIOA->PIO_ODR =
280 GPIO_FPGA_NINIT |
281 GPIO_FPGA_DONE;
282 // PIO controls the following pins
283 AT91C_BASE_PIOA->PIO_PER =
284 GPIO_FPGA_NINIT |
285 GPIO_FPGA_DONE;
286 // Enable pull-ups
287 AT91C_BASE_PIOA->PIO_PPUER =
288 GPIO_FPGA_NINIT |
289 GPIO_FPGA_DONE;
290
291 // setup initial logic state
292 HIGH(GPIO_FPGA_NPROGRAM);
293 LOW(GPIO_FPGA_CCLK);
294 LOW(GPIO_FPGA_DIN);
295 // These pins are outputs
296 AT91C_BASE_PIOA->PIO_OER =
297 GPIO_FPGA_NPROGRAM |
298 GPIO_FPGA_CCLK |
299 GPIO_FPGA_DIN;
300
301 // enter FPGA configuration mode
302 LOW(GPIO_FPGA_NPROGRAM);
303 SpinDelay(50);
304 HIGH(GPIO_FPGA_NPROGRAM);
305
306 i=100000;
307 // wait for FPGA ready to accept data signal
308 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
309 i--;
310 }
311
312 // crude error indicator, leave both red LEDs on and return
313 if (i==0){
314 LED_C_ON();
315 LED_D_ON();
316 return;
317 }
318
9783989b 319 for(i = 0; i < FpgaImageLen; i++) {
320 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
321 if (b < 0) {
322 Dbprintf("Error %d during FpgaDownload", b);
323 break;
15c4dc5a 324 }
9783989b 325 DownloadFPGA_byte(b);
15c4dc5a 326 }
9783989b 327
15c4dc5a 328 // continue to clock FPGA until ready signal goes high
329 i=100000;
330 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
331 HIGH(GPIO_FPGA_CCLK);
332 LOW(GPIO_FPGA_CCLK);
333 }
334 // crude error indicator, leave both red LEDs on and return
335 if (i==0){
336 LED_C_ON();
337 LED_D_ON();
338 return;
339 }
340 LED_D_OFF();
341}
342
9783989b 343
15c4dc5a 344/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
345 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
346 * After that the format is 1 byte section type (ASCII character), 2 byte length
347 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
348 * length.
349 */
9783989b 350static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 351{
15c4dc5a 352 int result = 0;
9783989b 353 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
354 uint16_t numbytes = 0;
355 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
356 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
357 numbytes++;
15c4dc5a 358 unsigned int current_length = 0;
359 if(current_name < 'a' || current_name > 'e') {
360 /* Strange section name, abort */
361 break;
362 }
363 current_length = 0;
364 switch(current_name) {
365 case 'e':
366 /* Four byte length field */
9783989b 367 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
368 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
369 numbytes += 2;
15c4dc5a 370 default: /* Fall through, two byte length field */
9783989b 371 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
372 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
373 numbytes += 2;
15c4dc5a 374 }
e30c654b 375
15c4dc5a 376 if(current_name != 'e' && current_length > 255) {
377 /* Maybe a parse error */
378 break;
379 }
e30c654b 380
15c4dc5a 381 if(current_name == section_name) {
382 /* Found it */
15c4dc5a 383 *section_length = current_length;
384 result = 1;
385 break;
386 }
e30c654b 387
9783989b 388 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
389 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
390 numbytes++;
391 }
15c4dc5a 392 }
e30c654b 393
15c4dc5a 394 return result;
395}
396
9783989b 397
398//----------------------------------------------------------------------------
399// Check which FPGA image is currently loaded (if any). If necessary
400// decompress and load the correct (HF or LF) image to the FPGA
401//----------------------------------------------------------------------------
7cc204bf 402void FpgaDownloadAndGo(int bitstream_version)
15c4dc5a 403{
9783989b 404 z_stream compressed_fpga_stream;
4a71da5a 405 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
9783989b 406
7cc204bf 407 // check whether or not the bitstream is already loaded
9783989b 408 if (downloaded_bitstream == bitstream_version)
7cc204bf 409 return;
410
9783989b 411 // make sure that we have enough memory to decompress
aaa1a9a2 412 BigBuf_free(); BigBuf_Clear_ext(false);
9783989b 413
414 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
7cc204bf 415 return;
15c4dc5a 416 }
e30c654b 417
9783989b 418 unsigned int bitstream_length;
419 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
420 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
421 downloaded_bitstream = bitstream_version;
422 }
15c4dc5a 423
9783989b 424 inflateEnd(&compressed_fpga_stream);
99cf19d9 425
aaa1a9a2 426 // free eventually allocated BigBuf memory
427 BigBuf_free(); BigBuf_Clear_ext(false);
9783989b 428}
7cc204bf 429
9783989b 430
431//-----------------------------------------------------------------------------
432// Gather version information from FPGA image. Needs to decompress the begin
433// of the respective (HF or LF) image.
434// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
435// advisable to call this only once and store the results for later use.
436//-----------------------------------------------------------------------------
437void FpgaGatherVersion(int bitstream_version, char *dst, int len)
15c4dc5a 438{
15c4dc5a 439 unsigned int fpga_info_len;
4a71da5a 440 char tempstr[40] = {0x00};
9783989b 441 z_stream compressed_fpga_stream;
4a71da5a 442 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
9783989b 443
444 dst[0] = '\0';
445
446 // ensure that we can allocate enough memory for decompression:
aaa1a9a2 447 BigBuf_free(); BigBuf_Clear_ext(false);
9783989b 448
4a71da5a 449 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
9783989b 450 return;
9783989b 451
452 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
453 for (uint16_t i = 0; i < fpga_info_len; i++) {
454 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
455 if (i < sizeof(tempstr)) {
456 tempstr[i] = c;
457 }
15c4dc5a 458 }
9783989b 459 if (!memcmp("fpga_lf", tempstr, 7))
460 strncat(dst, "LF ", len-1);
461 else if (!memcmp("fpga_hf", tempstr, 7))
462 strncat(dst, "HF ", len-1);
463 }
464 strncat(dst, "FPGA image built", len-1);
465 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
466 strncat(dst, " for ", len-1);
467 for (uint16_t i = 0; i < fpga_info_len; i++) {
468 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
469 if (i < sizeof(tempstr)) {
470 tempstr[i] = c;
471 }
15c4dc5a 472 }
9783989b 473 strncat(dst, tempstr, len-1);
474 }
475 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
476 strncat(dst, " on ", len-1);
477 for (uint16_t i = 0; i < fpga_info_len; i++) {
478 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
479 if (i < sizeof(tempstr)) {
480 tempstr[i] = c;
481 }
15c4dc5a 482 }
9783989b 483 strncat(dst, tempstr, len-1);
484 }
485 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
486 strncat(dst, " at ", len-1);
487 for (uint16_t i = 0; i < fpga_info_len; i++) {
488 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
489 if (i < sizeof(tempstr)) {
490 tempstr[i] = c;
491 }
15c4dc5a 492 }
9783989b 493 strncat(dst, tempstr, len-1);
15c4dc5a 494 }
9783989b 495
496 strncat(dst, "\n", len-1);
497
498 inflateEnd(&compressed_fpga_stream);
15c4dc5a 499}
500
9783989b 501
15c4dc5a 502//-----------------------------------------------------------------------------
503// Send a 16 bit command/data pair to the FPGA.
504// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
505// where C is the 4 bit command and D is the 12 bit data
506//-----------------------------------------------------------------------------
f7e3ed82 507void FpgaSendCommand(uint16_t cmd, uint16_t v)
15c4dc5a 508{
509 SetupSpi(SPI_FPGA_MODE);
510 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
511 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
512}
513//-----------------------------------------------------------------------------
514// Write the FPGA setup word (that determines what mode the logic is in, read
515// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
516// avoid changing this function's occurence everywhere in the source code.
517//-----------------------------------------------------------------------------
f7e3ed82 518void FpgaWriteConfWord(uint8_t v)
15c4dc5a 519{
520 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
521}
522
523//-----------------------------------------------------------------------------
524// Set up the CMOS switches that mux the ADC: four switches, independently
525// closable, but should only close one at a time. Not an FPGA thing, but
526// the samples from the ADC always flow through the FPGA.
527//-----------------------------------------------------------------------------
f7e3ed82 528void SetAdcMuxFor(uint32_t whichGpio)
15c4dc5a 529{
530 AT91C_BASE_PIOA->PIO_OER =
531 GPIO_MUXSEL_HIPKD |
532 GPIO_MUXSEL_LOPKD |
533 GPIO_MUXSEL_LORAW |
534 GPIO_MUXSEL_HIRAW;
535
536 AT91C_BASE_PIOA->PIO_PER =
537 GPIO_MUXSEL_HIPKD |
538 GPIO_MUXSEL_LOPKD |
539 GPIO_MUXSEL_LORAW |
540 GPIO_MUXSEL_HIRAW;
541
542 LOW(GPIO_MUXSEL_HIPKD);
543 LOW(GPIO_MUXSEL_HIRAW);
544 LOW(GPIO_MUXSEL_LORAW);
545 LOW(GPIO_MUXSEL_LOPKD);
546
547 HIGH(whichGpio);
548}
7838f4be 549
550void Fpga_print_status(void)
551{
552 Dbprintf("Fgpa");
553 if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf(" mode.............HF");
554 else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf(" mode.............LF");
555 else Dbprintf(" mode.............%d", downloaded_bitstream);
556}
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