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data psk demod minor fixes, pyramid demod add CS
[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
19
20
21/**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29{
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73}
74
75
76
77/* blank r/w tag data stream
78...0000000000000000 01111111
791010101010101010101010101010101010101010101010101010101010101010
800011010010100001
8101111111
82101010101010101[0]000...
83
84[5555fe852c5555555555555555fe0000]
85*/
86void ReadTItag(void)
87{
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
179 if (shift3 & (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214}
215
216void WriteTIbyte(uint8_t b)
217{
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239}
240
241void AcquireTiType(void)
242{
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN*32;
300 // unpack buffer
301 for (i=TIBUFLEN-1; i>=0; i--) {
302 for (j=0; j<32; j++) {
303 if(BigBuf[i] & (1 << j)) {
304 dest[--n] = 1;
305 } else {
306 dest[--n] = -1;
307 }
308 }
309 }
310}
311
312// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313// if crc provided, it will be written with the data verbatim (even if bogus)
314// if not provided a valid crc will be computed from the data and written.
315void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
316{
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
318 if(crc == 0) {
319 crc = update_crc16(crc, (idlo)&0xff);
320 crc = update_crc16(crc, (idlo>>8)&0xff);
321 crc = update_crc16(crc, (idlo>>16)&0xff);
322 crc = update_crc16(crc, (idlo>>24)&0xff);
323 crc = update_crc16(crc, (idhi)&0xff);
324 crc = update_crc16(crc, (idhi>>8)&0xff);
325 crc = update_crc16(crc, (idhi>>16)&0xff);
326 crc = update_crc16(crc, (idhi>>24)&0xff);
327 }
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use tiread to check");
382}
383
384void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385{
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 //wait until SSC_CLK goes HIGH
403 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
404 if(BUTTON_PRESS()) {
405 DbpString("Stopped");
406 return;
407 }
408 WDT_HIT();
409 }
410 if (ledcontrol)
411 LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol)
419 LED_D_OFF();
420 //wait until SSC_CLK goes LOW
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if(BUTTON_PRESS()) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431
432 i = 0;
433 if (gap) {
434 SHORT_COIL();
435 SpinDelayUs(gap);
436 }
437 }
438 }
439}
440
e09f21fa 441#define DEBUG_FRAME_CONTENTS 1
442void SimulateTagLowFrequencyBidir(int divisor, int t0)
443{
444}
445
446// compose fc/8 fc/10 waveform (FSK2)
447static void fc(int c, int *n)
448{
449 uint8_t *dest = BigBuf_get_addr();
450 int idx;
451
452 // for when we want an fc8 pattern every 4 logical bits
453 if(c==0) {
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 }
463
712ebfa6 464 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
e09f21fa 465 if(c==8) {
466 for (idx=0; idx<6; idx++) {
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 }
476 }
477
712ebfa6 478 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
e09f21fa 479 if(c==10) {
480 for (idx=0; idx<5; idx++) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 }
492 }
493}
494// compose fc/X fc/Y waveform (FSKx)
712ebfa6 495static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 496{
497 uint8_t *dest = BigBuf_get_addr();
712ebfa6 498 uint8_t halfFC = fc/2;
499 uint8_t wavesPerClock = clock/fc;
500 uint8_t mod = clock % fc; //modifier
501 uint8_t modAdj = fc/mod; //how often to apply modifier
502 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 503 // loop through clock - step field clock
712ebfa6 504 for (uint8_t idx=0; idx < wavesPerClock; idx++){
505 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
506 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
507 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
508 *n += fc;
e09f21fa 509 }
510 if (mod>0) (*modCnt)++;
511 if ((mod>0) && modAdjOk){ //fsk2
512 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 513 memset(dest+(*n), 0, fc-halfFC);
514 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
515 *n += fc;
e09f21fa 516 }
517 }
e09f21fa 518 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 519 memset(dest+(*n), 0, mod-(mod/2));
520 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
521 *n += mod;
e09f21fa 522 }
523}
524
525// prepare a waveform pattern in the buffer based on the ID given then
526// simulate a HID tag until the button is pressed
527void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
528{
529 int n=0, i=0;
530 /*
531 HID tag bitstream format
532 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
533 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
534 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
535 A fc8 is inserted before every 4 bits
536 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
537 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
538 */
539
540 if (hi>0xFFF) {
78f5b1a7 541 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 542 return;
543 }
544 fc(0,&n);
545 // special start of frame marker containing invalid bit sequences
546 fc(8, &n); fc(8, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548 fc(10, &n); fc(10, &n); // invalid
549 fc(8, &n); fc(10, &n); // logical 0
550
551 WDT_HIT();
552 // manchester encode bits 43 to 32
553 for (i=11; i>=0; i--) {
554 if ((i%4)==3) fc(0,&n);
555 if ((hi>>i)&1) {
556 fc(10, &n); fc(8, &n); // low-high transition
557 } else {
558 fc(8, &n); fc(10, &n); // high-low transition
559 }
560 }
561
562 WDT_HIT();
563 // manchester encode bits 31 to 0
564 for (i=31; i>=0; i--) {
565 if ((i%4)==3) fc(0,&n);
566 if ((lo>>i)&1) {
567 fc(10, &n); fc(8, &n); // low-high transition
568 } else {
569 fc(8, &n); fc(10, &n); // high-low transition
570 }
571 }
572
573 if (ledcontrol)
574 LED_A_ON();
575 SimulateTagLowFrequency(n, 0, ledcontrol);
576
577 if (ledcontrol)
578 LED_A_OFF();
579}
580
581// prepare a waveform pattern in the buffer based on the ID given then
582// simulate a FSK tag until the button is pressed
583// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
584void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
585{
586 int ledcontrol=1;
587 int n=0, i=0;
588 uint8_t fcHigh = arg1 >> 8;
589 uint8_t fcLow = arg1 & 0xFF;
590 uint16_t modCnt = 0;
e09f21fa 591 uint8_t clk = arg2 & 0xFF;
592 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 593
e09f21fa 594 for (i=0; i<size; i++){
595 if (BitStream[i] == invert){
596 fcAll(fcLow, &n, clk, &modCnt);
597 } else {
598 fcAll(fcHigh, &n, clk, &modCnt);
599 }
600 }
601 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 602 /*Dbprintf("DEBUG: First 32:");
e09f21fa 603 uint8_t *dest = BigBuf_get_addr();
604 i=0;
605 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
606 i+=16;
607 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 608 */
e09f21fa 609 if (ledcontrol)
610 LED_A_ON();
712ebfa6 611
78f5b1a7 612 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 613
614 if (ledcontrol)
615 LED_A_OFF();
616}
617
618// compose ask waveform for one bit(ASK)
619static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
620{
621 uint8_t *dest = BigBuf_get_addr();
712ebfa6 622 uint8_t halfClk = clock/2;
e09f21fa 623 // c = current bit 1 or 0
712ebfa6 624 if (manchester){
625 memset(dest+(*n), c, halfClk);
626 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 627 } else {
712ebfa6 628 memset(dest+(*n), c, clock);
e09f21fa 629 }
712ebfa6 630 *n += clock;
e09f21fa 631}
632
633// args clock, ask/man or askraw, invert, transmission separator
634void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
635{
636 int ledcontrol = 1;
637 int n=0, i=0;
638 uint8_t clk = (arg1 >> 8) & 0xFF;
639 uint8_t manchester = arg1 & 1;
640 uint8_t separator = arg2 & 1;
641 uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 642 for (i=0; i<size; i++){
643 askSimBit(BitStream[i]^invert, &n, clk, manchester);
644 }
ada339a1 645 if (manchester==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
646 for (i=0; i<size; i++){
647 askSimBit(BitStream[i]^invert^1, &n, clk, manchester);
648 }
649 }
712ebfa6 650 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 651
652 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
653 //DEBUG
712ebfa6 654 //Dbprintf("First 32:");
e09f21fa 655 //uint8_t *dest = BigBuf_get_addr();
656 //i=0;
657 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
658 //i+=16;
659 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 660
661 if (ledcontrol)
662 LED_A_ON();
712ebfa6 663
78f5b1a7 664 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 665
666 if (ledcontrol)
667 LED_A_OFF();
668}
669
670//carrier can be 2,4 or 8
671static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
672{
673 uint8_t *dest = BigBuf_get_addr();
712ebfa6 674 uint8_t halfWave = waveLen/2;
675 //uint8_t idx;
e09f21fa 676 int i = 0;
677 if (phaseChg){
678 // write phase change
712ebfa6 679 memset(dest+(*n), *curPhase^1, halfWave);
680 memset(dest+(*n) + halfWave, *curPhase, halfWave);
681 *n += waveLen;
e09f21fa 682 *curPhase ^= 1;
712ebfa6 683 i += waveLen;
e09f21fa 684 }
685 //write each normal clock wave for the clock duration
686 for (; i < clk; i+=waveLen){
712ebfa6 687 memset(dest+(*n), *curPhase, halfWave);
688 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
689 *n += waveLen;
e09f21fa 690 }
691}
692
693// args clock, carrier, invert,
694void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
695{
696 int ledcontrol=1;
697 int n=0, i=0;
698 uint8_t clk = arg1 >> 8;
699 uint8_t carrier = arg1 & 0xFF;
700 uint8_t invert = arg2 & 0xFF;
78f5b1a7 701 uint8_t curPhase = 0;
e09f21fa 702 for (i=0; i<size; i++){
703 if (BitStream[i] == curPhase){
704 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
705 } else {
706 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
707 }
708 }
709 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 710 //Dbprintf("DEBUG: First 32:");
711 //uint8_t *dest = BigBuf_get_addr();
712 //i=0;
713 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
714 //i+=16;
715 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 716
717 if (ledcontrol)
718 LED_A_ON();
78f5b1a7 719 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 720
721 if (ledcontrol)
722 LED_A_OFF();
723}
724
725// loop to get raw HID waveform then FSK demodulate the TAG ID from it
726void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
727{
728 uint8_t *dest = BigBuf_get_addr();
729 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
730 size_t size = 0;
731 uint32_t hi2=0, hi=0, lo=0;
732 int idx=0;
733 // Configure to go in 125Khz listen mode
734 LFSetupFPGAForADC(95, true);
735
736 while(!BUTTON_PRESS()) {
737
738 WDT_HIT();
739 if (ledcontrol) LED_A_ON();
740
741 DoAcquisition_default(-1,true);
742 // FSK demodulator
743 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
744 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
745
746 if (idx>0 && lo>0){
747 // final loop, go over previously decoded manchester data and decode into usable tag ID
748 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
749 if (hi2 != 0){ //extra large HID tags
750 Dbprintf("TAG ID: %x%08x%08x (%d)",
751 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
752 }else { //standard HID tags <38 bits
753 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
754 uint8_t bitlen = 0;
755 uint32_t fc = 0;
756 uint32_t cardnum = 0;
757 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
758 uint32_t lo2=0;
759 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
760 uint8_t idx3 = 1;
761 while(lo2 > 1){ //find last bit set to 1 (format len bit)
762 lo2=lo2 >> 1;
763 idx3++;
764 }
765 bitlen = idx3+19;
766 fc =0;
767 cardnum=0;
768 if(bitlen == 26){
769 cardnum = (lo>>1)&0xFFFF;
770 fc = (lo>>17)&0xFF;
771 }
772 if(bitlen == 37){
773 cardnum = (lo>>1)&0x7FFFF;
774 fc = ((hi&0xF)<<12)|(lo>>20);
775 }
776 if(bitlen == 34){
777 cardnum = (lo>>1)&0xFFFF;
778 fc= ((hi&1)<<15)|(lo>>17);
779 }
780 if(bitlen == 35){
781 cardnum = (lo>>1)&0xFFFFF;
782 fc = ((hi&1)<<11)|(lo>>21);
783 }
784 }
785 else { //if bit 38 is not set then 37 bit format is used
786 bitlen= 37;
787 fc =0;
788 cardnum=0;
789 if(bitlen==37){
790 cardnum = (lo>>1)&0x7FFFF;
791 fc = ((hi&0xF)<<12)|(lo>>20);
792 }
793 }
794 //Dbprintf("TAG ID: %x%08x (%d)",
795 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
796 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
797 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
798 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
799 }
800 if (findone){
801 if (ledcontrol) LED_A_OFF();
802 *high = hi;
803 *low = lo;
804 return;
805 }
806 // reset
807 hi2 = hi = lo = 0;
808 }
809 WDT_HIT();
810 }
811 DbpString("Stopped");
812 if (ledcontrol) LED_A_OFF();
813}
814
815void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
816{
817 uint8_t *dest = BigBuf_get_addr();
818
819 size_t size=0, idx=0;
820 int clk=0, invert=0, errCnt=0, maxErr=20;
821 uint64_t lo=0;
822 // Configure to go in 125Khz listen mode
823 LFSetupFPGAForADC(95, true);
824
825 while(!BUTTON_PRESS()) {
826
827 WDT_HIT();
828 if (ledcontrol) LED_A_ON();
829
830 DoAcquisition_default(-1,true);
831 size = BigBuf_max_traceLen();
832 //Dbprintf("DEBUG: Buffer got");
833 //askdemod and manchester decode
834 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
835 //Dbprintf("DEBUG: ASK Got");
836 WDT_HIT();
837
838 if (errCnt>=0){
839 lo = Em410xDecode(dest, &size, &idx);
840 //Dbprintf("DEBUG: EM GOT");
841 if (lo>0){
842 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
843 (uint32_t)(lo>>32),
844 (uint32_t)lo,
845 (uint32_t)(lo&0xFFFF),
846 (uint32_t)((lo>>16LL) & 0xFF),
847 (uint32_t)(lo & 0xFFFFFF));
848 }
849 if (findone){
850 if (ledcontrol) LED_A_OFF();
851 *high=lo>>32;
852 *low=lo & 0xFFFFFFFF;
853 return;
854 }
855 } else{
856 //Dbprintf("DEBUG: No Tag");
857 }
858 WDT_HIT();
859 lo = 0;
860 clk=0;
861 invert=0;
862 errCnt=0;
863 size=0;
864 }
865 DbpString("Stopped");
866 if (ledcontrol) LED_A_OFF();
867}
868
869void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
870{
871 uint8_t *dest = BigBuf_get_addr();
872 int idx=0;
873 uint32_t code=0, code2=0;
874 uint8_t version=0;
875 uint8_t facilitycode=0;
876 uint16_t number=0;
877 // Configure to go in 125Khz listen mode
878 LFSetupFPGAForADC(95, true);
879
880 while(!BUTTON_PRESS()) {
881 WDT_HIT();
882 if (ledcontrol) LED_A_ON();
883 DoAcquisition_default(-1,true);
884 //fskdemod and get start index
885 WDT_HIT();
886 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
887 if (idx>0){
888 //valid tag found
889
890 //Index map
891 //0 10 20 30 40 50 60
892 //| | | | | | |
893 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
894 //-----------------------------------------------------------------------------
895 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
896 //
897 //XSF(version)facility:codeone+codetwo
898 //Handle the data
899 if(findone){ //only print binary if we are doing one
900 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
901 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
902 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
903 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
904 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
905 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
906 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
907 }
908 code = bytebits_to_byte(dest+idx,32);
909 code2 = bytebits_to_byte(dest+idx+32,32);
910 version = bytebits_to_byte(dest+idx+27,8); //14,4
911 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
912 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
913
914 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
915 // if we're only looking for one tag
916 if (findone){
917 if (ledcontrol) LED_A_OFF();
918 //LED_A_OFF();
919 *high=code;
920 *low=code2;
921 return;
922 }
923 code=code2=0;
924 version=facilitycode=0;
925 number=0;
926 idx=0;
927 }
928 WDT_HIT();
929 }
930 DbpString("Stopped");
931 if (ledcontrol) LED_A_OFF();
932}
933
934/*------------------------------
935 * T5555/T5557/T5567 routines
936 *------------------------------
937 */
938
939/* T55x7 configuration register definitions */
940#define T55x7_POR_DELAY 0x00000001
941#define T55x7_ST_TERMINATOR 0x00000008
942#define T55x7_PWD 0x00000010
943#define T55x7_MAXBLOCK_SHIFT 5
944#define T55x7_AOR 0x00000200
945#define T55x7_PSKCF_RF_2 0
946#define T55x7_PSKCF_RF_4 0x00000400
947#define T55x7_PSKCF_RF_8 0x00000800
948#define T55x7_MODULATION_DIRECT 0
949#define T55x7_MODULATION_PSK1 0x00001000
950#define T55x7_MODULATION_PSK2 0x00002000
951#define T55x7_MODULATION_PSK3 0x00003000
952#define T55x7_MODULATION_FSK1 0x00004000
953#define T55x7_MODULATION_FSK2 0x00005000
954#define T55x7_MODULATION_FSK1a 0x00006000
955#define T55x7_MODULATION_FSK2a 0x00007000
956#define T55x7_MODULATION_MANCHESTER 0x00008000
957#define T55x7_MODULATION_BIPHASE 0x00010000
958#define T55x7_BITRATE_RF_8 0
959#define T55x7_BITRATE_RF_16 0x00040000
960#define T55x7_BITRATE_RF_32 0x00080000
961#define T55x7_BITRATE_RF_40 0x000C0000
962#define T55x7_BITRATE_RF_50 0x00100000
963#define T55x7_BITRATE_RF_64 0x00140000
964#define T55x7_BITRATE_RF_100 0x00180000
965#define T55x7_BITRATE_RF_128 0x001C0000
966
967/* T5555 (Q5) configuration register definitions */
968#define T5555_ST_TERMINATOR 0x00000001
969#define T5555_MAXBLOCK_SHIFT 0x00000001
970#define T5555_MODULATION_MANCHESTER 0
971#define T5555_MODULATION_PSK1 0x00000010
972#define T5555_MODULATION_PSK2 0x00000020
973#define T5555_MODULATION_PSK3 0x00000030
974#define T5555_MODULATION_FSK1 0x00000040
975#define T5555_MODULATION_FSK2 0x00000050
976#define T5555_MODULATION_BIPHASE 0x00000060
977#define T5555_MODULATION_DIRECT 0x00000070
978#define T5555_INVERT_OUTPUT 0x00000080
979#define T5555_PSK_RF_2 0
980#define T5555_PSK_RF_4 0x00000100
981#define T5555_PSK_RF_8 0x00000200
982#define T5555_USE_PWD 0x00000400
983#define T5555_USE_AOR 0x00000800
984#define T5555_BITRATE_SHIFT 12
985#define T5555_FAST_WRITE 0x00004000
986#define T5555_PAGE_SELECT 0x00008000
987
988/*
989 * Relevant times in microsecond
990 * To compensate antenna falling times shorten the write times
991 * and enlarge the gap ones.
992 */
993#define START_GAP 250
994#define WRITE_GAP 160
995#define WRITE_0 144 // 192
996#define WRITE_1 400 // 432 for T55x7; 448 for E5550
997
998// Write one bit to card
999void T55xxWriteBit(int bit)
1000{
1001 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1002 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1003 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1004 if (bit == 0)
1005 SpinDelayUs(WRITE_0);
1006 else
1007 SpinDelayUs(WRITE_1);
1008 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1009 SpinDelayUs(WRITE_GAP);
1010}
1011
1012// Write one card block in page 0, no lock
1013void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1014{
1015 //unsigned int i; //enio adjustment 12/10/14
1016 uint32_t i;
1017
1018 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1019 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1020 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1021
1022 // Give it a bit of time for the resonant antenna to settle.
1023 // And for the tag to fully power up
1024 SpinDelay(150);
1025
1026 // Now start writting
1027 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1028 SpinDelayUs(START_GAP);
1029
1030 // Opcode
1031 T55xxWriteBit(1);
1032 T55xxWriteBit(0); //Page 0
1033 if (PwdMode == 1){
1034 // Pwd
1035 for (i = 0x80000000; i != 0; i >>= 1)
1036 T55xxWriteBit(Pwd & i);
1037 }
1038 // Lock bit
1039 T55xxWriteBit(0);
1040
1041 // Data
1042 for (i = 0x80000000; i != 0; i >>= 1)
1043 T55xxWriteBit(Data & i);
1044
1045 // Block
1046 for (i = 0x04; i != 0; i >>= 1)
1047 T55xxWriteBit(Block & i);
1048
1049 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1050 // so wait a little more)
1051 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1052 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1053 SpinDelay(20);
1054 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1055}
1056
1057// Read one card block in page 0
1058void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1059{
1060 uint8_t *dest = BigBuf_get_addr();
1061 //int m=0, i=0; //enio adjustment 12/10/14
1062 uint32_t m=0, i=0;
1063 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1064 m = BigBuf_max_traceLen();
1065 // Clear destination buffer before sending the command
1066 memset(dest, 128, m);
1067 // Connect the A/D to the peak-detected low-frequency path.
1068 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1069 // Now set up the SSC to get the ADC samples that are now streaming at us.
1070 FpgaSetupSsc();
1071
1072 LED_D_ON();
1073 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1075
1076 // Give it a bit of time for the resonant antenna to settle.
1077 // And for the tag to fully power up
1078 SpinDelay(150);
1079
1080 // Now start writting
1081 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1082 SpinDelayUs(START_GAP);
1083
1084 // Opcode
1085 T55xxWriteBit(1);
1086 T55xxWriteBit(0); //Page 0
1087 if (PwdMode == 1){
1088 // Pwd
1089 for (i = 0x80000000; i != 0; i >>= 1)
1090 T55xxWriteBit(Pwd & i);
1091 }
1092 // Lock bit
1093 T55xxWriteBit(0);
1094 // Block
1095 for (i = 0x04; i != 0; i >>= 1)
1096 T55xxWriteBit(Block & i);
1097
1098 // Turn field on to read the response
1099 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1100 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1101
1102 // Now do the acquisition
1103 i = 0;
1104 for(;;) {
1105 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1106 AT91C_BASE_SSC->SSC_THR = 0x43;
1107 }
1108 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1109 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1110 // we don't care about actual value, only if it's more or less than a
1111 // threshold essentially we capture zero crossings for later analysis
1112 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1113 i++;
1114 if (i >= m) break;
1115 }
1116 }
1117
1118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1119 LED_D_OFF();
1120 DbpString("DONE!");
1121}
1122
1123// Read card traceability data (page 1)
1124void T55xxReadTrace(void){
1125 uint8_t *dest = BigBuf_get_addr();
1126 int m=0, i=0;
1127
1128 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1129 m = BigBuf_max_traceLen();
1130 // Clear destination buffer before sending the command
1131 memset(dest, 128, m);
1132 // Connect the A/D to the peak-detected low-frequency path.
1133 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1134 // Now set up the SSC to get the ADC samples that are now streaming at us.
1135 FpgaSetupSsc();
1136
1137 LED_D_ON();
1138 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1139 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1140
1141 // Give it a bit of time for the resonant antenna to settle.
1142 // And for the tag to fully power up
1143 SpinDelay(150);
1144
1145 // Now start writting
1146 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1147 SpinDelayUs(START_GAP);
1148
1149 // Opcode
1150 T55xxWriteBit(1);
1151 T55xxWriteBit(1); //Page 1
1152
1153 // Turn field on to read the response
1154 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1156
1157 // Now do the acquisition
1158 i = 0;
1159 for(;;) {
1160 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1161 AT91C_BASE_SSC->SSC_THR = 0x43;
1162 }
1163 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1164 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1165 i++;
1166 if (i >= m) break;
1167 }
1168 }
1169
1170 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1171 LED_D_OFF();
1172 DbpString("DONE!");
1173}
1174
1175/*-------------- Cloning routines -----------*/
1176// Copy HID id to card and setup block 0 config
1177void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1178{
1179 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1180 int last_block = 0;
1181
1182 if (longFMT){
1183 // Ensure no more than 84 bits supplied
1184 if (hi2>0xFFFFF) {
1185 DbpString("Tags can only have 84 bits.");
1186 return;
1187 }
1188 // Build the 6 data blocks for supplied 84bit ID
1189 last_block = 6;
1190 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1191 for (int i=0;i<4;i++) {
1192 if (hi2 & (1<<(19-i)))
1193 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1194 else
1195 data1 |= (1<<((3-i)*2)); // 0 -> 01
1196 }
1197
1198 data2 = 0;
1199 for (int i=0;i<16;i++) {
1200 if (hi2 & (1<<(15-i)))
1201 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1202 else
1203 data2 |= (1<<((15-i)*2)); // 0 -> 01
1204 }
1205
1206 data3 = 0;
1207 for (int i=0;i<16;i++) {
1208 if (hi & (1<<(31-i)))
1209 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1210 else
1211 data3 |= (1<<((15-i)*2)); // 0 -> 01
1212 }
1213
1214 data4 = 0;
1215 for (int i=0;i<16;i++) {
1216 if (hi & (1<<(15-i)))
1217 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1218 else
1219 data4 |= (1<<((15-i)*2)); // 0 -> 01
1220 }
1221
1222 data5 = 0;
1223 for (int i=0;i<16;i++) {
1224 if (lo & (1<<(31-i)))
1225 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1226 else
1227 data5 |= (1<<((15-i)*2)); // 0 -> 01
1228 }
1229
1230 data6 = 0;
1231 for (int i=0;i<16;i++) {
1232 if (lo & (1<<(15-i)))
1233 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1234 else
1235 data6 |= (1<<((15-i)*2)); // 0 -> 01
1236 }
1237 }
1238 else {
1239 // Ensure no more than 44 bits supplied
1240 if (hi>0xFFF) {
1241 DbpString("Tags can only have 44 bits.");
1242 return;
1243 }
1244
1245 // Build the 3 data blocks for supplied 44bit ID
1246 last_block = 3;
1247
1248 data1 = 0x1D000000; // load preamble
1249
1250 for (int i=0;i<12;i++) {
1251 if (hi & (1<<(11-i)))
1252 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1253 else
1254 data1 |= (1<<((11-i)*2)); // 0 -> 01
1255 }
1256
1257 data2 = 0;
1258 for (int i=0;i<16;i++) {
1259 if (lo & (1<<(31-i)))
1260 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1261 else
1262 data2 |= (1<<((15-i)*2)); // 0 -> 01
1263 }
1264
1265 data3 = 0;
1266 for (int i=0;i<16;i++) {
1267 if (lo & (1<<(15-i)))
1268 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1269 else
1270 data3 |= (1<<((15-i)*2)); // 0 -> 01
1271 }
1272 }
1273
1274 LED_D_ON();
1275 // Program the data blocks for supplied ID
1276 // and the block 0 for HID format
1277 T55xxWriteBlock(data1,1,0,0);
1278 T55xxWriteBlock(data2,2,0,0);
1279 T55xxWriteBlock(data3,3,0,0);
1280
1281 if (longFMT) { // if long format there are 6 blocks
1282 T55xxWriteBlock(data4,4,0,0);
1283 T55xxWriteBlock(data5,5,0,0);
1284 T55xxWriteBlock(data6,6,0,0);
1285 }
1286
1287 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1288 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1289 T55x7_MODULATION_FSK2a |
1290 last_block << T55x7_MAXBLOCK_SHIFT,
1291 0,0,0);
1292
1293 LED_D_OFF();
1294
1295 DbpString("DONE!");
1296}
1297
1298void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1299{
1300 int data1=0, data2=0; //up to six blocks for long format
1301
1302 data1 = hi; // load preamble
1303 data2 = lo;
1304
1305 LED_D_ON();
1306 // Program the data blocks for supplied ID
1307 // and the block 0 for HID format
1308 T55xxWriteBlock(data1,1,0,0);
1309 T55xxWriteBlock(data2,2,0,0);
1310
1311 //Config Block
1312 T55xxWriteBlock(0x00147040,0,0,0);
1313 LED_D_OFF();
1314
1315 DbpString("DONE!");
1316}
1317
1318// Define 9bit header for EM410x tags
1319#define EM410X_HEADER 0x1FF
1320#define EM410X_ID_LENGTH 40
1321
1322void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1323{
1324 int i, id_bit;
1325 uint64_t id = EM410X_HEADER;
1326 uint64_t rev_id = 0; // reversed ID
1327 int c_parity[4]; // column parity
1328 int r_parity = 0; // row parity
1329 uint32_t clock = 0;
1330
1331 // Reverse ID bits given as parameter (for simpler operations)
1332 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1333 if (i < 32) {
1334 rev_id = (rev_id << 1) | (id_lo & 1);
1335 id_lo >>= 1;
1336 } else {
1337 rev_id = (rev_id << 1) | (id_hi & 1);
1338 id_hi >>= 1;
1339 }
1340 }
1341
1342 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1343 id_bit = rev_id & 1;
1344
1345 if (i % 4 == 0) {
1346 // Don't write row parity bit at start of parsing
1347 if (i)
1348 id = (id << 1) | r_parity;
1349 // Start counting parity for new row
1350 r_parity = id_bit;
1351 } else {
1352 // Count row parity
1353 r_parity ^= id_bit;
1354 }
1355
1356 // First elements in column?
1357 if (i < 4)
1358 // Fill out first elements
1359 c_parity[i] = id_bit;
1360 else
1361 // Count column parity
1362 c_parity[i % 4] ^= id_bit;
1363
1364 // Insert ID bit
1365 id = (id << 1) | id_bit;
1366 rev_id >>= 1;
1367 }
1368
1369 // Insert parity bit of last row
1370 id = (id << 1) | r_parity;
1371
1372 // Fill out column parity at the end of tag
1373 for (i = 0; i < 4; ++i)
1374 id = (id << 1) | c_parity[i];
1375
1376 // Add stop bit
1377 id <<= 1;
1378
1379 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1380 LED_D_ON();
1381
1382 // Write EM410x ID
1383 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1384 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1385
1386 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1387 if (card) {
1388 // Clock rate is stored in bits 8-15 of the card value
1389 clock = (card & 0xFF00) >> 8;
1390 Dbprintf("Clock rate: %d", clock);
1391 switch (clock)
1392 {
1393 case 32:
1394 clock = T55x7_BITRATE_RF_32;
1395 break;
1396 case 16:
1397 clock = T55x7_BITRATE_RF_16;
1398 break;
1399 case 0:
1400 // A value of 0 is assumed to be 64 for backwards-compatibility
1401 // Fall through...
1402 case 64:
1403 clock = T55x7_BITRATE_RF_64;
1404 break;
1405 default:
1406 Dbprintf("Invalid clock rate: %d", clock);
1407 return;
1408 }
1409
1410 // Writing configuration for T55x7 tag
1411 T55xxWriteBlock(clock |
1412 T55x7_MODULATION_MANCHESTER |
1413 2 << T55x7_MAXBLOCK_SHIFT,
1414 0, 0, 0);
1415 }
1416 else
1417 // Writing configuration for T5555(Q5) tag
1418 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1419 T5555_MODULATION_MANCHESTER |
1420 2 << T5555_MAXBLOCK_SHIFT,
1421 0, 0, 0);
1422
1423 LED_D_OFF();
1424 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1425 (uint32_t)(id >> 32), (uint32_t)id);
1426}
1427
1428// Clone Indala 64-bit tag by UID to T55x7
1429void CopyIndala64toT55x7(int hi, int lo)
1430{
1431
1432 //Program the 2 data blocks for supplied 64bit UID
1433 // and the block 0 for Indala64 format
1434 T55xxWriteBlock(hi,1,0,0);
1435 T55xxWriteBlock(lo,2,0,0);
1436 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1437 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1438 T55x7_MODULATION_PSK1 |
1439 2 << T55x7_MAXBLOCK_SHIFT,
1440 0, 0, 0);
1441 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1442 // T5567WriteBlock(0x603E1042,0);
1443
1444 DbpString("DONE!");
1445
1446}
1447
1448void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1449{
1450
1451 //Program the 7 data blocks for supplied 224bit UID
1452 // and the block 0 for Indala224 format
1453 T55xxWriteBlock(uid1,1,0,0);
1454 T55xxWriteBlock(uid2,2,0,0);
1455 T55xxWriteBlock(uid3,3,0,0);
1456 T55xxWriteBlock(uid4,4,0,0);
1457 T55xxWriteBlock(uid5,5,0,0);
1458 T55xxWriteBlock(uid6,6,0,0);
1459 T55xxWriteBlock(uid7,7,0,0);
1460 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1461 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1462 T55x7_MODULATION_PSK1 |
1463 7 << T55x7_MAXBLOCK_SHIFT,
1464 0,0,0);
1465 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1466 // T5567WriteBlock(0x603E10E2,0);
1467
1468 DbpString("DONE!");
1469
1470}
1471
1472
1473#define abs(x) ( ((x)<0) ? -(x) : (x) )
1474#define max(x,y) ( x<y ? y:x)
1475
1476int DemodPCF7931(uint8_t **outBlocks) {
1477 uint8_t BitStream[256];
1478 uint8_t Blocks[8][16];
1479 uint8_t *GraphBuffer = BigBuf_get_addr();
1480 int GraphTraceLen = BigBuf_max_traceLen();
1481 int i, j, lastval, bitidx, half_switch;
1482 int clock = 64;
1483 int tolerance = clock / 8;
1484 int pmc, block_done;
1485 int lc, warnings = 0;
1486 int num_blocks = 0;
1487 int lmin=128, lmax=128;
1488 uint8_t dir;
1489
1490 LFSetupFPGAForADC(95, true);
1491 DoAcquisition_default(0, 0);
1492
1493
1494 lmin = 64;
1495 lmax = 192;
1496
1497 i = 2;
1498
1499 /* Find first local max/min */
1500 if(GraphBuffer[1] > GraphBuffer[0]) {
1501 while(i < GraphTraceLen) {
1502 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1503 break;
1504 i++;
1505 }
1506 dir = 0;
1507 }
1508 else {
1509 while(i < GraphTraceLen) {
1510 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1511 break;
1512 i++;
1513 }
1514 dir = 1;
1515 }
1516
1517 lastval = i++;
1518 half_switch = 0;
1519 pmc = 0;
1520 block_done = 0;
1521
1522 for (bitidx = 0; i < GraphTraceLen; i++)
1523 {
1524 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1525 {
1526 lc = i - lastval;
1527 lastval = i;
1528
1529 // Switch depending on lc length:
1530 // Tolerance is 1/8 of clock rate (arbitrary)
1531 if (abs(lc-clock/4) < tolerance) {
1532 // 16T0
1533 if((i - pmc) == lc) { /* 16T0 was previous one */
1534 /* It's a PMC ! */
1535 i += (128+127+16+32+33+16)-1;
1536 lastval = i;
1537 pmc = 0;
1538 block_done = 1;
1539 }
1540 else {
1541 pmc = i;
1542 }
1543 } else if (abs(lc-clock/2) < tolerance) {
1544 // 32TO
1545 if((i - pmc) == lc) { /* 16T0 was previous one */
1546 /* It's a PMC ! */
1547 i += (128+127+16+32+33)-1;
1548 lastval = i;
1549 pmc = 0;
1550 block_done = 1;
1551 }
1552 else if(half_switch == 1) {
1553 BitStream[bitidx++] = 0;
1554 half_switch = 0;
1555 }
1556 else
1557 half_switch++;
1558 } else if (abs(lc-clock) < tolerance) {
1559 // 64TO
1560 BitStream[bitidx++] = 1;
1561 } else {
1562 // Error
1563 warnings++;
1564 if (warnings > 10)
1565 {
1566 Dbprintf("Error: too many detection errors, aborting.");
1567 return 0;
1568 }
1569 }
1570
1571 if(block_done == 1) {
1572 if(bitidx == 128) {
1573 for(j=0; j<16; j++) {
1574 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1575 64*BitStream[j*8+6]+
1576 32*BitStream[j*8+5]+
1577 16*BitStream[j*8+4]+
1578 8*BitStream[j*8+3]+
1579 4*BitStream[j*8+2]+
1580 2*BitStream[j*8+1]+
1581 BitStream[j*8];
1582 }
1583 num_blocks++;
1584 }
1585 bitidx = 0;
1586 block_done = 0;
1587 half_switch = 0;
1588 }
1589 if(i < GraphTraceLen)
1590 {
1591 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1592 else dir = 1;
1593 }
1594 }
1595 if(bitidx==255)
1596 bitidx=0;
1597 warnings = 0;
1598 if(num_blocks == 4) break;
1599 }
1600 memcpy(outBlocks, Blocks, 16*num_blocks);
1601 return num_blocks;
1602}
1603
1604int IsBlock0PCF7931(uint8_t *Block) {
1605 // Assume RFU means 0 :)
1606 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1607 return 1;
1608 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1609 return 1;
1610 return 0;
1611}
1612
1613int IsBlock1PCF7931(uint8_t *Block) {
1614 // Assume RFU means 0 :)
1615 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1616 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1617 return 1;
1618
1619 return 0;
1620}
1621
1622#define ALLOC 16
1623
1624void ReadPCF7931() {
1625 uint8_t Blocks[8][17];
1626 uint8_t tmpBlocks[4][16];
1627 int i, j, ind, ind2, n;
1628 int num_blocks = 0;
1629 int max_blocks = 8;
1630 int ident = 0;
1631 int error = 0;
1632 int tries = 0;
1633
1634 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1635
1636 do {
1637 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1638 n = DemodPCF7931((uint8_t**)tmpBlocks);
1639 if(!n)
1640 error++;
1641 if(error==10 && num_blocks == 0) {
1642 Dbprintf("Error, no tag or bad tag");
1643 return;
1644 }
1645 else if (tries==20 || error==10) {
1646 Dbprintf("Error reading the tag");
1647 Dbprintf("Here is the partial content");
1648 goto end;
1649 }
1650
1651 for(i=0; i<n; i++)
1652 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1653 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1654 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1655 if(!ident) {
1656 for(i=0; i<n; i++) {
1657 if(IsBlock0PCF7931(tmpBlocks[i])) {
1658 // Found block 0 ?
1659 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1660 // Found block 1!
1661 // \o/
1662 ident = 1;
1663 memcpy(Blocks[0], tmpBlocks[i], 16);
1664 Blocks[0][ALLOC] = 1;
1665 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1666 Blocks[1][ALLOC] = 1;
1667 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1668 // Debug print
1669 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1670 num_blocks = 2;
1671 // Handle following blocks
1672 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1673 if(j==n) j=0;
1674 if(j==i) break;
1675 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1676 Blocks[ind2][ALLOC] = 1;
1677 }
1678 break;
1679 }
1680 }
1681 }
1682 }
1683 else {
1684 for(i=0; i<n; i++) { // Look for identical block in known blocks
1685 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1686 for(j=0; j<max_blocks; j++) {
1687 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1688 // Found an identical block
1689 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1690 if(ind2 < 0)
1691 ind2 = max_blocks;
1692 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1693 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1694 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1695 Blocks[ind2][ALLOC] = 1;
1696 num_blocks++;
1697 if(num_blocks == max_blocks) goto end;
1698 }
1699 }
1700 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1701 if(ind2 > max_blocks)
1702 ind2 = 0;
1703 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1704 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1705 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1706 Blocks[ind2][ALLOC] = 1;
1707 num_blocks++;
1708 if(num_blocks == max_blocks) goto end;
1709 }
1710 }
1711 }
1712 }
1713 }
1714 }
1715 }
1716 tries++;
1717 if (BUTTON_PRESS()) return;
1718 } while (num_blocks != max_blocks);
1719 end:
1720 Dbprintf("-----------------------------------------");
1721 Dbprintf("Memory content:");
1722 Dbprintf("-----------------------------------------");
1723 for(i=0; i<max_blocks; i++) {
1724 if(Blocks[i][ALLOC]==1)
1725 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1726 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1727 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1728 else
1729 Dbprintf("<missing block %d>", i);
1730 }
1731 Dbprintf("-----------------------------------------");
1732
1733 return ;
1734}
1735
1736
1737//-----------------------------------
1738// EM4469 / EM4305 routines
1739//-----------------------------------
1740#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1741#define FWD_CMD_WRITE 0xA
1742#define FWD_CMD_READ 0x9
1743#define FWD_CMD_DISABLE 0x5
1744
1745
1746uint8_t forwardLink_data[64]; //array of forwarded bits
1747uint8_t * forward_ptr; //ptr for forward message preparation
1748uint8_t fwd_bit_sz; //forwardlink bit counter
1749uint8_t * fwd_write_ptr; //forwardlink bit pointer
1750
1751//====================================================================
1752// prepares command bits
1753// see EM4469 spec
1754//====================================================================
1755//--------------------------------------------------------------------
1756uint8_t Prepare_Cmd( uint8_t cmd ) {
1757 //--------------------------------------------------------------------
1758
1759 *forward_ptr++ = 0; //start bit
1760 *forward_ptr++ = 0; //second pause for 4050 code
1761
1762 *forward_ptr++ = cmd;
1763 cmd >>= 1;
1764 *forward_ptr++ = cmd;
1765 cmd >>= 1;
1766 *forward_ptr++ = cmd;
1767 cmd >>= 1;
1768 *forward_ptr++ = cmd;
1769
1770 return 6; //return number of emited bits
1771}
1772
1773//====================================================================
1774// prepares address bits
1775// see EM4469 spec
1776//====================================================================
1777
1778//--------------------------------------------------------------------
1779uint8_t Prepare_Addr( uint8_t addr ) {
1780 //--------------------------------------------------------------------
1781
1782 register uint8_t line_parity;
1783
1784 uint8_t i;
1785 line_parity = 0;
1786 for(i=0;i<6;i++) {
1787 *forward_ptr++ = addr;
1788 line_parity ^= addr;
1789 addr >>= 1;
1790 }
1791
1792 *forward_ptr++ = (line_parity & 1);
1793
1794 return 7; //return number of emited bits
1795}
1796
1797//====================================================================
1798// prepares data bits intreleaved with parity bits
1799// see EM4469 spec
1800//====================================================================
1801
1802//--------------------------------------------------------------------
1803uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1804 //--------------------------------------------------------------------
1805
1806 register uint8_t line_parity;
1807 register uint8_t column_parity;
1808 register uint8_t i, j;
1809 register uint16_t data;
1810
1811 data = data_low;
1812 column_parity = 0;
1813
1814 for(i=0; i<4; i++) {
1815 line_parity = 0;
1816 for(j=0; j<8; j++) {
1817 line_parity ^= data;
1818 column_parity ^= (data & 1) << j;
1819 *forward_ptr++ = data;
1820 data >>= 1;
1821 }
1822 *forward_ptr++ = line_parity;
1823 if(i == 1)
1824 data = data_hi;
1825 }
1826
1827 for(j=0; j<8; j++) {
1828 *forward_ptr++ = column_parity;
1829 column_parity >>= 1;
1830 }
1831 *forward_ptr = 0;
1832
1833 return 45; //return number of emited bits
1834}
1835
1836//====================================================================
1837// Forward Link send function
1838// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1839// fwd_bit_count set with number of bits to be sent
1840//====================================================================
1841void SendForward(uint8_t fwd_bit_count) {
1842
1843 fwd_write_ptr = forwardLink_data;
1844 fwd_bit_sz = fwd_bit_count;
1845
1846 LED_D_ON();
1847
1848 //Field on
1849 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1850 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1851 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1852
1853 // Give it a bit of time for the resonant antenna to settle.
1854 // And for the tag to fully power up
1855 SpinDelay(150);
1856
1857 // force 1st mod pulse (start gap must be longer for 4305)
1858 fwd_bit_sz--; //prepare next bit modulation
1859 fwd_write_ptr++;
1860 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1861 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1862 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1863 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1864 SpinDelayUs(16*8); //16 cycles on (8us each)
1865
1866 // now start writting
1867 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1868 if(((*fwd_write_ptr++) & 1) == 1)
1869 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1870 else {
1871 //These timings work for 4469/4269/4305 (with the 55*8 above)
1872 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1873 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1874 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1875 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1876 SpinDelayUs(9*8); //16 cycles on (8us each)
1877 }
1878 }
1879}
1880
1881void EM4xLogin(uint32_t Password) {
1882
1883 uint8_t fwd_bit_count;
1884
1885 forward_ptr = forwardLink_data;
1886 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1887 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1888
1889 SendForward(fwd_bit_count);
1890
1891 //Wait for command to complete
1892 SpinDelay(20);
1893
1894}
1895
1896void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1897
1898 uint8_t fwd_bit_count;
1899 uint8_t *dest = BigBuf_get_addr();
1900 int m=0, i=0;
1901
1902 //If password mode do login
1903 if (PwdMode == 1) EM4xLogin(Pwd);
1904
1905 forward_ptr = forwardLink_data;
1906 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1907 fwd_bit_count += Prepare_Addr( Address );
1908
1909 m = BigBuf_max_traceLen();
1910 // Clear destination buffer before sending the command
1911 memset(dest, 128, m);
1912 // Connect the A/D to the peak-detected low-frequency path.
1913 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1914 // Now set up the SSC to get the ADC samples that are now streaming at us.
1915 FpgaSetupSsc();
1916
1917 SendForward(fwd_bit_count);
1918
1919 // Now do the acquisition
1920 i = 0;
1921 for(;;) {
1922 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1923 AT91C_BASE_SSC->SSC_THR = 0x43;
1924 }
1925 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1926 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1927 i++;
1928 if (i >= m) break;
1929 }
1930 }
1931 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1932 LED_D_OFF();
1933}
1934
1935void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1936
1937 uint8_t fwd_bit_count;
1938
1939 //If password mode do login
1940 if (PwdMode == 1) EM4xLogin(Pwd);
1941
1942 forward_ptr = forwardLink_data;
1943 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1944 fwd_bit_count += Prepare_Addr( Address );
1945 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1946
1947 SendForward(fwd_bit_count);
1948
1949 //Wait for write to complete
1950 SpinDelay(20);
1951 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1952 LED_D_OFF();
1953}
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