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Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "usb_cdc.h"
20
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
213 }
214
215 void WriteTIbyte(uint8_t b)
216 {
217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
238 }
239
240 void AcquireTiType(void)
241 {
242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
245 #define TIBUFLEN 1250
246
247 // clear buffer
248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
249 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
297 char *dest = (char *)BigBuf_get_addr();
298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
309 }
310
311 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312 // if crc provided, it will be written with the data verbatim (even if bogus)
313 // if not provided a valid crc will be computed from the data and written.
314 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
315 {
316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use tiread to check");
381 }
382
383 void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
384 {
385 int i;
386 uint8_t *tab = BigBuf_get_addr();
387
388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
390
391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
392
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || usb_poll()) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol)
410 LED_D_ON();
411
412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
416
417 if (ledcontrol)
418 LED_D_OFF();
419 //wait until SSC_CLK goes LOW
420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
426 }
427
428 i++;
429 if(i == period) {
430
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
502 // loop through clock - step field clock
503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
515 }
516 }
517 if (mod>0 && !modAdjOk){ //fsk1
518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
521 }
522 }
523
524 // prepare a waveform pattern in the buffer based on the ID given then
525 // simulate a HID tag until the button is pressed
526 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527 {
528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
578 }
579
580 // prepare a waveform pattern in the buffer based on the ID given then
581 // simulate a FSK tag until the button is pressed
582 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584 {
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
592
593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
601 /*Dbprintf("DEBUG: First 32:");
602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 */
608 if (ledcontrol)
609 LED_A_ON();
610
611 SimulateTagLowFrequency(n, 0, ledcontrol);
612
613 if (ledcontrol)
614 LED_A_OFF();
615 }
616
617 // compose ask waveform for one bit(ASK)
618 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619 {
620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 // c = current bit 1 or 0
623 if (manchester==1){
624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
626 } else {
627 memset(dest+(*n), c, clock);
628 }
629 *n += clock;
630 }
631
632 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
633 {
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 if (c){
637 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
638 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
639 } else {
640 memset(dest+(*n), c ^ *phase, clock);
641 *phase ^= 1;
642 }
643
644 }
645
646 // args clock, ask/man or askraw, invert, transmission separator
647 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
648 {
649 int ledcontrol = 1;
650 int n=0, i=0;
651 uint8_t clk = (arg1 >> 8) & 0xFF;
652 uint8_t encoding = arg1 & 1;
653 uint8_t separator = arg2 & 1;
654 uint8_t invert = (arg2 >> 8) & 1;
655
656 if (encoding==2){ //biphase
657 uint8_t phase=0;
658 for (i=0; i<size; i++){
659 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
660 }
661 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
662 for (i=0; i<size; i++){
663 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
664 }
665 }
666 } else { // ask/manchester || ask/raw
667 for (i=0; i<size; i++){
668 askSimBit(BitStream[i]^invert, &n, clk, encoding);
669 }
670 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
671 for (i=0; i<size; i++){
672 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
673 }
674 }
675 }
676
677 if (separator==1) Dbprintf("sorry but separator option not yet available");
678
679 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
680 //DEBUG
681 //Dbprintf("First 32:");
682 //uint8_t *dest = BigBuf_get_addr();
683 //i=0;
684 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
685 //i+=16;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687
688 if (ledcontrol)
689 LED_A_ON();
690
691 SimulateTagLowFrequency(n, 0, ledcontrol);
692
693 if (ledcontrol)
694 LED_A_OFF();
695 }
696
697 //carrier can be 2,4 or 8
698 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
699 {
700 uint8_t *dest = BigBuf_get_addr();
701 uint8_t halfWave = waveLen/2;
702 //uint8_t idx;
703 int i = 0;
704 if (phaseChg){
705 // write phase change
706 memset(dest+(*n), *curPhase^1, halfWave);
707 memset(dest+(*n) + halfWave, *curPhase, halfWave);
708 *n += waveLen;
709 *curPhase ^= 1;
710 i += waveLen;
711 }
712 //write each normal clock wave for the clock duration
713 for (; i < clk; i+=waveLen){
714 memset(dest+(*n), *curPhase, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
716 *n += waveLen;
717 }
718 }
719
720 // args clock, carrier, invert,
721 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
722 {
723 int ledcontrol=1;
724 int n=0, i=0;
725 uint8_t clk = arg1 >> 8;
726 uint8_t carrier = arg1 & 0xFF;
727 uint8_t invert = arg2 & 0xFF;
728 uint8_t curPhase = 0;
729 for (i=0; i<size; i++){
730 if (BitStream[i] == curPhase){
731 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
732 } else {
733 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
734 }
735 }
736 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
737 //Dbprintf("DEBUG: First 32:");
738 //uint8_t *dest = BigBuf_get_addr();
739 //i=0;
740 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
741 //i+=16;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743
744 if (ledcontrol)
745 LED_A_ON();
746 SimulateTagLowFrequency(n, 0, ledcontrol);
747
748 if (ledcontrol)
749 LED_A_OFF();
750 }
751
752 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
753 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
754 {
755 uint8_t *dest = BigBuf_get_addr();
756 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
757 size_t size = 0;
758 uint32_t hi2=0, hi=0, lo=0;
759 int idx=0;
760 // Configure to go in 125Khz listen mode
761 LFSetupFPGAForADC(95, true);
762
763 while(!BUTTON_PRESS()) {
764
765 WDT_HIT();
766 if (ledcontrol) LED_A_ON();
767
768 DoAcquisition_default(-1,true);
769 // FSK demodulator
770 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
771 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
772
773 if (idx>0 && lo>0){
774 // final loop, go over previously decoded manchester data and decode into usable tag ID
775 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
776 if (hi2 != 0){ //extra large HID tags
777 Dbprintf("TAG ID: %x%08x%08x (%d)",
778 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
779 }else { //standard HID tags <38 bits
780 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
781 uint8_t bitlen = 0;
782 uint32_t fc = 0;
783 uint32_t cardnum = 0;
784 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
785 uint32_t lo2=0;
786 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
787 uint8_t idx3 = 1;
788 while(lo2 > 1){ //find last bit set to 1 (format len bit)
789 lo2=lo2 >> 1;
790 idx3++;
791 }
792 bitlen = idx3+19;
793 fc =0;
794 cardnum=0;
795 if(bitlen == 26){
796 cardnum = (lo>>1)&0xFFFF;
797 fc = (lo>>17)&0xFF;
798 }
799 if(bitlen == 37){
800 cardnum = (lo>>1)&0x7FFFF;
801 fc = ((hi&0xF)<<12)|(lo>>20);
802 }
803 if(bitlen == 34){
804 cardnum = (lo>>1)&0xFFFF;
805 fc= ((hi&1)<<15)|(lo>>17);
806 }
807 if(bitlen == 35){
808 cardnum = (lo>>1)&0xFFFFF;
809 fc = ((hi&1)<<11)|(lo>>21);
810 }
811 }
812 else { //if bit 38 is not set then 37 bit format is used
813 bitlen= 37;
814 fc =0;
815 cardnum=0;
816 if(bitlen==37){
817 cardnum = (lo>>1)&0x7FFFF;
818 fc = ((hi&0xF)<<12)|(lo>>20);
819 }
820 }
821 //Dbprintf("TAG ID: %x%08x (%d)",
822 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
823 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
824 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
825 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
826 }
827 if (findone){
828 if (ledcontrol) LED_A_OFF();
829 *high = hi;
830 *low = lo;
831 return;
832 }
833 // reset
834 hi2 = hi = lo = 0;
835 }
836 WDT_HIT();
837 }
838 DbpString("Stopped");
839 if (ledcontrol) LED_A_OFF();
840 }
841
842 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
843 {
844 uint8_t *dest = BigBuf_get_addr();
845
846 size_t size=0, idx=0;
847 int clk=0, invert=0, errCnt=0, maxErr=20;
848 uint32_t hi=0;
849 uint64_t lo=0;
850 // Configure to go in 125Khz listen mode
851 LFSetupFPGAForADC(95, true);
852
853 while(!BUTTON_PRESS()) {
854
855 WDT_HIT();
856 if (ledcontrol) LED_A_ON();
857
858 DoAcquisition_default(-1,true);
859 size = BigBuf_max_traceLen();
860 //Dbprintf("DEBUG: Buffer got");
861 //askdemod and manchester decode
862 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
863 //Dbprintf("DEBUG: ASK Got");
864 WDT_HIT();
865
866 if (errCnt>=0){
867 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
868 //Dbprintf("DEBUG: EM GOT");
869 if (errCnt){
870 if (size>64){
871 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
872 hi,
873 (uint32_t)(lo>>32),
874 (uint32_t)lo,
875 (uint32_t)(lo&0xFFFF),
876 (uint32_t)((lo>>16LL) & 0xFF),
877 (uint32_t)(lo & 0xFFFFFF));
878 } else {
879 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
880 (uint32_t)(lo>>32),
881 (uint32_t)lo,
882 (uint32_t)(lo&0xFFFF),
883 (uint32_t)((lo>>16LL) & 0xFF),
884 (uint32_t)(lo & 0xFFFFFF));
885 }
886 }
887 if (findone){
888 if (ledcontrol) LED_A_OFF();
889 *high=lo>>32;
890 *low=lo & 0xFFFFFFFF;
891 return;
892 }
893 } else{
894 //Dbprintf("DEBUG: No Tag");
895 }
896 WDT_HIT();
897 lo = 0;
898 clk=0;
899 invert=0;
900 errCnt=0;
901 size=0;
902 }
903 DbpString("Stopped");
904 if (ledcontrol) LED_A_OFF();
905 }
906
907 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
908 {
909 uint8_t *dest = BigBuf_get_addr();
910 int idx=0;
911 uint32_t code=0, code2=0;
912 uint8_t version=0;
913 uint8_t facilitycode=0;
914 uint16_t number=0;
915 uint8_t crc = 0;
916 uint16_t calccrc = 0;
917 // Configure to go in 125Khz listen mode
918 LFSetupFPGAForADC(95, true);
919
920 while(!BUTTON_PRESS()) {
921 WDT_HIT();
922 if (ledcontrol) LED_A_ON();
923 DoAcquisition_default(-1,true);
924 //fskdemod and get start index
925 WDT_HIT();
926 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
927 if (idx>0){
928 //valid tag found
929
930 //Index map
931 //0 10 20 30 40 50 60
932 //| | | | | | |
933 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
934 //-----------------------------------------------------------------------------
935 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
936 //
937 //Checksum:
938 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
939 //preamble F0 E0 01 03 B6 75
940 // How to calc checksum,
941 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
942 // F0 + E0 + 01 + 03 + B6 = 28A
943 // 28A & FF = 8A
944 // FF - 8A = 75
945 // Checksum: 0x75
946 //XSF(version)facility:codeone+codetwo
947 //Handle the data
948 if(findone){ //only print binary if we are doing one
949 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
950 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
951 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
952 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
953 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
954 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
955 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
956 }
957 code = bytebits_to_byte(dest+idx,32);
958 code2 = bytebits_to_byte(dest+idx+32,32);
959 version = bytebits_to_byte(dest+idx+27,8); //14,4
960 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
961 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
962
963 crc = bytebits_to_byte(dest+idx+54,8);
964 for (uint8_t i=1; i<6; ++i)
965 calccrc += bytebits_to_byte(dest+idx+9*i,8);
966 calccrc &= 0xff;
967 calccrc = 0xff - calccrc;
968
969 char *crcStr = (crc == calccrc) ? "ok":"!crc";
970
971 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
972 // if we're only looking for one tag
973 if (findone){
974 if (ledcontrol) LED_A_OFF();
975 //LED_A_OFF();
976 *high=code;
977 *low=code2;
978 return;
979 }
980 code=code2=0;
981 version=facilitycode=0;
982 number=0;
983 idx=0;
984 }
985 WDT_HIT();
986 }
987 DbpString("Stopped");
988 if (ledcontrol) LED_A_OFF();
989 }
990
991 /*------------------------------
992 * T5555/T5557/T5567 routines
993 *------------------------------
994 */
995
996 /* T55x7 configuration register definitions */
997 #define T55x7_POR_DELAY 0x00000001
998 #define T55x7_ST_TERMINATOR 0x00000008
999 #define T55x7_PWD 0x00000010
1000 #define T55x7_MAXBLOCK_SHIFT 5
1001 #define T55x7_AOR 0x00000200
1002 #define T55x7_PSKCF_RF_2 0
1003 #define T55x7_PSKCF_RF_4 0x00000400
1004 #define T55x7_PSKCF_RF_8 0x00000800
1005 #define T55x7_MODULATION_DIRECT 0
1006 #define T55x7_MODULATION_PSK1 0x00001000
1007 #define T55x7_MODULATION_PSK2 0x00002000
1008 #define T55x7_MODULATION_PSK3 0x00003000
1009 #define T55x7_MODULATION_FSK1 0x00004000
1010 #define T55x7_MODULATION_FSK2 0x00005000
1011 #define T55x7_MODULATION_FSK1a 0x00006000
1012 #define T55x7_MODULATION_FSK2a 0x00007000
1013 #define T55x7_MODULATION_MANCHESTER 0x00008000
1014 #define T55x7_MODULATION_BIPHASE 0x00010000
1015 #define T55x7_BITRATE_RF_8 0
1016 #define T55x7_BITRATE_RF_16 0x00040000
1017 #define T55x7_BITRATE_RF_32 0x00080000
1018 #define T55x7_BITRATE_RF_40 0x000C0000
1019 #define T55x7_BITRATE_RF_50 0x00100000
1020 #define T55x7_BITRATE_RF_64 0x00140000
1021 #define T55x7_BITRATE_RF_100 0x00180000
1022 #define T55x7_BITRATE_RF_128 0x001C0000
1023
1024 /* T5555 (Q5) configuration register definitions */
1025 #define T5555_ST_TERMINATOR 0x00000001
1026 #define T5555_MAXBLOCK_SHIFT 0x00000001
1027 #define T5555_MODULATION_MANCHESTER 0
1028 #define T5555_MODULATION_PSK1 0x00000010
1029 #define T5555_MODULATION_PSK2 0x00000020
1030 #define T5555_MODULATION_PSK3 0x00000030
1031 #define T5555_MODULATION_FSK1 0x00000040
1032 #define T5555_MODULATION_FSK2 0x00000050
1033 #define T5555_MODULATION_BIPHASE 0x00000060
1034 #define T5555_MODULATION_DIRECT 0x00000070
1035 #define T5555_INVERT_OUTPUT 0x00000080
1036 #define T5555_PSK_RF_2 0
1037 #define T5555_PSK_RF_4 0x00000100
1038 #define T5555_PSK_RF_8 0x00000200
1039 #define T5555_USE_PWD 0x00000400
1040 #define T5555_USE_AOR 0x00000800
1041 #define T5555_BITRATE_SHIFT 12
1042 #define T5555_FAST_WRITE 0x00004000
1043 #define T5555_PAGE_SELECT 0x00008000
1044
1045 /*
1046 * Relevant times in microsecond
1047 * To compensate antenna falling times shorten the write times
1048 * and enlarge the gap ones.
1049 */
1050 #define START_GAP 50*8 // 10 - 50fc 250
1051 #define WRITE_GAP 20*8 // 8 - 30fc
1052 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
1053 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1054
1055 // VALUES TAKEN FROM EM4x function: SendForward
1056 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1057 // WRITE_GAP = 128; (16*8)
1058 // WRITE_1 = 256 32*8; (32*8)
1059
1060 // These timings work for 4469/4269/4305 (with the 55*8 above)
1061 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1062
1063 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1064 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1065 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1066 // T0 = TIMER_CLOCK1 / 125000 = 192
1067 // 1 Cycle = 8 microseconds(us)
1068
1069 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1070
1071 // Write one bit to card
1072 void T55xxWriteBit(int bit)
1073 {
1074 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1075 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1076 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1077 if (!bit)
1078 SpinDelayUs(WRITE_0);
1079 else
1080 SpinDelayUs(WRITE_1);
1081 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1082 SpinDelayUs(WRITE_GAP);
1083 }
1084
1085 // Write one card block in page 0, no lock
1086 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1087 {
1088 uint32_t i = 0;
1089
1090 // Set up FPGA, 125kHz
1091 // Wait for config.. (192+8190xPOW)x8 == 67ms
1092 LFSetupFPGAForADC(0, true);
1093
1094 // Now start writting
1095 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1096 SpinDelayUs(START_GAP);
1097
1098 // Opcode
1099 T55xxWriteBit(1);
1100 T55xxWriteBit(0); //Page 0
1101 if (PwdMode == 1){
1102 // Pwd
1103 for (i = 0x80000000; i != 0; i >>= 1)
1104 T55xxWriteBit(Pwd & i);
1105 }
1106 // Lock bit
1107 T55xxWriteBit(0);
1108
1109 // Data
1110 for (i = 0x80000000; i != 0; i >>= 1)
1111 T55xxWriteBit(Data & i);
1112
1113 // Block
1114 for (i = 0x04; i != 0; i >>= 1)
1115 T55xxWriteBit(Block & i);
1116
1117 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1118 // so wait a little more)
1119 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1120 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1121 SpinDelay(20);
1122 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1123 }
1124
1125 void TurnReadLFOn(){
1126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1127 // Give it a bit of time for the resonant antenna to settle.
1128 SpinDelayUs(8*150);
1129 }
1130
1131
1132 // Read one card block in page 0
1133 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1134 {
1135 uint32_t i = 0;
1136 uint8_t *dest = BigBuf_get_addr();
1137 uint16_t bufferlength = BigBuf_max_traceLen();
1138 if ( bufferlength > T55xx_SAMPLES_SIZE )
1139 bufferlength = T55xx_SAMPLES_SIZE;
1140
1141 // Clear destination buffer before sending the command
1142 memset(dest, 0x80, bufferlength);
1143
1144 // Set up FPGA, 125kHz
1145 // Wait for config.. (192+8190xPOW)x8 == 67ms
1146 LFSetupFPGAForADC(0, true);
1147 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1148 SpinDelayUs(START_GAP);
1149
1150 // Opcode
1151 T55xxWriteBit(1);
1152 T55xxWriteBit(0); //Page 0
1153 if (PwdMode == 1){
1154 // Pwd
1155 for (i = 0x80000000; i != 0; i >>= 1)
1156 T55xxWriteBit(Pwd & i);
1157 }
1158 // Lock bit
1159 T55xxWriteBit(0);
1160 // Block
1161 for (i = 0x04; i != 0; i >>= 1)
1162 T55xxWriteBit(Block & i);
1163
1164 // Turn field on to read the response
1165 TurnReadLFOn();
1166 // Now do the acquisition
1167 i = 0;
1168 for(;;) {
1169 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1170 AT91C_BASE_SSC->SSC_THR = 0x43;
1171 LED_D_ON();
1172 }
1173 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1174 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1175 i++;
1176 LED_D_OFF();
1177 if (i >= bufferlength) break;
1178 }
1179 }
1180
1181 cmd_send(CMD_ACK,0,0,0,0,0);
1182 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1183 LED_D_OFF();
1184 }
1185
1186 // Read card traceability data (page 1)
1187 void T55xxReadTrace(void){
1188
1189 uint32_t i = 0;
1190 uint8_t *dest = BigBuf_get_addr();
1191 uint16_t bufferlength = BigBuf_max_traceLen();
1192 if ( bufferlength > T55xx_SAMPLES_SIZE )
1193 bufferlength= T55xx_SAMPLES_SIZE;
1194
1195 // Clear destination buffer before sending the command
1196 memset(dest, 0x80, bufferlength);
1197
1198 LFSetupFPGAForADC(0, true);
1199 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1200 SpinDelayUs(START_GAP);
1201
1202 // Opcode
1203 T55xxWriteBit(1);
1204 T55xxWriteBit(1); //Page 1
1205
1206 // Turn field on to read the response
1207 TurnReadLFOn();
1208
1209 // Now do the acquisition
1210 for(;;) {
1211 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1212 AT91C_BASE_SSC->SSC_THR = 0x43;
1213 LED_D_ON();
1214 }
1215 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1216 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1217 i++;
1218 LED_D_OFF();
1219
1220 if (i >= bufferlength) break;
1221 }
1222 }
1223
1224 cmd_send(CMD_ACK,0,0,0,0,0);
1225 cmd_send(CMD_ACK,0,0,0,0,0);
1226 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1227 LED_D_OFF();
1228 }
1229
1230 void TurnReadLFOn(){
1231 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1232 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1233 // Give it a bit of time for the resonant antenna to settle.
1234 //SpinDelay(30);
1235 SpinDelayUs(8*150);
1236 }
1237
1238 /*-------------- Cloning routines -----------*/
1239 // Copy HID id to card and setup block 0 config
1240 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1241 {
1242 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1243 int last_block = 0;
1244
1245 if (longFMT){
1246 // Ensure no more than 84 bits supplied
1247 if (hi2>0xFFFFF) {
1248 DbpString("Tags can only have 84 bits.");
1249 return;
1250 }
1251 // Build the 6 data blocks for supplied 84bit ID
1252 last_block = 6;
1253 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1254 for (int i=0;i<4;i++) {
1255 if (hi2 & (1<<(19-i)))
1256 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1257 else
1258 data1 |= (1<<((3-i)*2)); // 0 -> 01
1259 }
1260
1261 data2 = 0;
1262 for (int i=0;i<16;i++) {
1263 if (hi2 & (1<<(15-i)))
1264 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1265 else
1266 data2 |= (1<<((15-i)*2)); // 0 -> 01
1267 }
1268
1269 data3 = 0;
1270 for (int i=0;i<16;i++) {
1271 if (hi & (1<<(31-i)))
1272 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1273 else
1274 data3 |= (1<<((15-i)*2)); // 0 -> 01
1275 }
1276
1277 data4 = 0;
1278 for (int i=0;i<16;i++) {
1279 if (hi & (1<<(15-i)))
1280 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1281 else
1282 data4 |= (1<<((15-i)*2)); // 0 -> 01
1283 }
1284
1285 data5 = 0;
1286 for (int i=0;i<16;i++) {
1287 if (lo & (1<<(31-i)))
1288 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1289 else
1290 data5 |= (1<<((15-i)*2)); // 0 -> 01
1291 }
1292
1293 data6 = 0;
1294 for (int i=0;i<16;i++) {
1295 if (lo & (1<<(15-i)))
1296 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1297 else
1298 data6 |= (1<<((15-i)*2)); // 0 -> 01
1299 }
1300 }
1301 else {
1302 // Ensure no more than 44 bits supplied
1303 if (hi>0xFFF) {
1304 DbpString("Tags can only have 44 bits.");
1305 return;
1306 }
1307
1308 // Build the 3 data blocks for supplied 44bit ID
1309 last_block = 3;
1310
1311 data1 = 0x1D000000; // load preamble
1312
1313 for (int i=0;i<12;i++) {
1314 if (hi & (1<<(11-i)))
1315 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1316 else
1317 data1 |= (1<<((11-i)*2)); // 0 -> 01
1318 }
1319
1320 data2 = 0;
1321 for (int i=0;i<16;i++) {
1322 if (lo & (1<<(31-i)))
1323 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1324 else
1325 data2 |= (1<<((15-i)*2)); // 0 -> 01
1326 }
1327
1328 data3 = 0;
1329 for (int i=0;i<16;i++) {
1330 if (lo & (1<<(15-i)))
1331 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1332 else
1333 data3 |= (1<<((15-i)*2)); // 0 -> 01
1334 }
1335 }
1336
1337 LED_D_ON();
1338 // Program the data blocks for supplied ID
1339 // and the block 0 for HID format
1340 T55xxWriteBlock(data1,1,0,0);
1341 T55xxWriteBlock(data2,2,0,0);
1342 T55xxWriteBlock(data3,3,0,0);
1343
1344 if (longFMT) { // if long format there are 6 blocks
1345 T55xxWriteBlock(data4,4,0,0);
1346 T55xxWriteBlock(data5,5,0,0);
1347 T55xxWriteBlock(data6,6,0,0);
1348 }
1349
1350 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1351 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1352 T55x7_MODULATION_FSK2a |
1353 last_block << T55x7_MAXBLOCK_SHIFT,
1354 0,0,0);
1355
1356 LED_D_OFF();
1357
1358 DbpString("DONE!");
1359 }
1360
1361 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1362 {
1363 int data1=0, data2=0; //up to six blocks for long format
1364
1365 data1 = hi; // load preamble
1366 data2 = lo;
1367
1368 LED_D_ON();
1369 // Program the data blocks for supplied ID
1370 // and the block 0 for HID format
1371 T55xxWriteBlock(data1,1,0,0);
1372 T55xxWriteBlock(data2,2,0,0);
1373
1374 //Config Block
1375 T55xxWriteBlock(0x00147040,0,0,0);
1376 LED_D_OFF();
1377
1378 DbpString("DONE!");
1379 }
1380
1381 // Define 9bit header for EM410x tags
1382 #define EM410X_HEADER 0x1FF
1383 #define EM410X_ID_LENGTH 40
1384
1385 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1386 {
1387 int i, id_bit;
1388 uint64_t id = EM410X_HEADER;
1389 uint64_t rev_id = 0; // reversed ID
1390 int c_parity[4]; // column parity
1391 int r_parity = 0; // row parity
1392 uint32_t clock = 0;
1393
1394 // Reverse ID bits given as parameter (for simpler operations)
1395 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1396 if (i < 32) {
1397 rev_id = (rev_id << 1) | (id_lo & 1);
1398 id_lo >>= 1;
1399 } else {
1400 rev_id = (rev_id << 1) | (id_hi & 1);
1401 id_hi >>= 1;
1402 }
1403 }
1404
1405 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1406 id_bit = rev_id & 1;
1407
1408 if (i % 4 == 0) {
1409 // Don't write row parity bit at start of parsing
1410 if (i)
1411 id = (id << 1) | r_parity;
1412 // Start counting parity for new row
1413 r_parity = id_bit;
1414 } else {
1415 // Count row parity
1416 r_parity ^= id_bit;
1417 }
1418
1419 // First elements in column?
1420 if (i < 4)
1421 // Fill out first elements
1422 c_parity[i] = id_bit;
1423 else
1424 // Count column parity
1425 c_parity[i % 4] ^= id_bit;
1426
1427 // Insert ID bit
1428 id = (id << 1) | id_bit;
1429 rev_id >>= 1;
1430 }
1431
1432 // Insert parity bit of last row
1433 id = (id << 1) | r_parity;
1434
1435 // Fill out column parity at the end of tag
1436 for (i = 0; i < 4; ++i)
1437 id = (id << 1) | c_parity[i];
1438
1439 // Add stop bit
1440 id <<= 1;
1441
1442 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1443 LED_D_ON();
1444
1445 // Write EM410x ID
1446 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1447 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1448
1449 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1450 if (card) {
1451 // Clock rate is stored in bits 8-15 of the card value
1452 clock = (card & 0xFF00) >> 8;
1453 Dbprintf("Clock rate: %d", clock);
1454 switch (clock)
1455 {
1456 case 32:
1457 clock = T55x7_BITRATE_RF_32;
1458 break;
1459 case 16:
1460 clock = T55x7_BITRATE_RF_16;
1461 break;
1462 case 0:
1463 // A value of 0 is assumed to be 64 for backwards-compatibility
1464 // Fall through...
1465 case 64:
1466 clock = T55x7_BITRATE_RF_64;
1467 break;
1468 default:
1469 Dbprintf("Invalid clock rate: %d", clock);
1470 return;
1471 }
1472
1473 // Writing configuration for T55x7 tag
1474 T55xxWriteBlock(clock |
1475 T55x7_MODULATION_MANCHESTER |
1476 2 << T55x7_MAXBLOCK_SHIFT,
1477 0, 0, 0);
1478 }
1479 else
1480 // Writing configuration for T5555(Q5) tag
1481 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1482 T5555_MODULATION_MANCHESTER |
1483 2 << T5555_MAXBLOCK_SHIFT,
1484 0, 0, 0);
1485
1486 LED_D_OFF();
1487 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1488 (uint32_t)(id >> 32), (uint32_t)id);
1489 }
1490
1491 // Clone Indala 64-bit tag by UID to T55x7
1492 void CopyIndala64toT55x7(int hi, int lo)
1493 {
1494
1495 //Program the 2 data blocks for supplied 64bit UID
1496 // and the block 0 for Indala64 format
1497 T55xxWriteBlock(hi,1,0,0);
1498 T55xxWriteBlock(lo,2,0,0);
1499 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1500 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1501 T55x7_MODULATION_PSK1 |
1502 2 << T55x7_MAXBLOCK_SHIFT,
1503 0, 0, 0);
1504 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1505 // T5567WriteBlock(0x603E1042,0);
1506
1507 DbpString("DONE!");
1508
1509 }
1510
1511 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1512 {
1513
1514 //Program the 7 data blocks for supplied 224bit UID
1515 // and the block 0 for Indala224 format
1516 T55xxWriteBlock(uid1,1,0,0);
1517 T55xxWriteBlock(uid2,2,0,0);
1518 T55xxWriteBlock(uid3,3,0,0);
1519 T55xxWriteBlock(uid4,4,0,0);
1520 T55xxWriteBlock(uid5,5,0,0);
1521 T55xxWriteBlock(uid6,6,0,0);
1522 T55xxWriteBlock(uid7,7,0,0);
1523 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1524 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1525 T55x7_MODULATION_PSK1 |
1526 7 << T55x7_MAXBLOCK_SHIFT,
1527 0,0,0);
1528 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1529 // T5567WriteBlock(0x603E10E2,0);
1530
1531 DbpString("DONE!");
1532
1533 }
1534
1535
1536 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1537 #define max(x,y) ( x<y ? y:x)
1538
1539 int DemodPCF7931(uint8_t **outBlocks) {
1540
1541 uint8_t bits[256] = {0x00};
1542 uint8_t blocks[8][16];
1543 uint8_t *dest = BigBuf_get_addr();
1544
1545 int GraphTraceLen = BigBuf_max_traceLen();
1546 if ( GraphTraceLen > 18000 )
1547 GraphTraceLen = 18000;
1548
1549
1550 int i, j, lastval, bitidx, half_switch;
1551 int clock = 64;
1552 int tolerance = clock / 8;
1553 int pmc, block_done;
1554 int lc, warnings = 0;
1555 int num_blocks = 0;
1556 int lmin=128, lmax=128;
1557 uint8_t dir;
1558
1559 LFSetupFPGAForADC(95, true);
1560 DoAcquisition_default(0, true);
1561
1562 lmin = 64;
1563 lmax = 192;
1564
1565 i = 2;
1566
1567 /* Find first local max/min */
1568 if(dest[1] > dest[0]) {
1569 while(i < GraphTraceLen) {
1570 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
1571 break;
1572 i++;
1573 }
1574 dir = 0;
1575 }
1576 else {
1577 while(i < GraphTraceLen) {
1578 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
1579 break;
1580 i++;
1581 }
1582 dir = 1;
1583 }
1584
1585 lastval = i++;
1586 half_switch = 0;
1587 pmc = 0;
1588 block_done = 0;
1589
1590 for (bitidx = 0; i < GraphTraceLen; i++)
1591 {
1592 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
1593 {
1594 lc = i - lastval;
1595 lastval = i;
1596
1597 // Switch depending on lc length:
1598 // Tolerance is 1/8 of clock rate (arbitrary)
1599 if (abs(lc-clock/4) < tolerance) {
1600 // 16T0
1601 if((i - pmc) == lc) { /* 16T0 was previous one */
1602 /* It's a PMC ! */
1603 i += (128+127+16+32+33+16)-1;
1604 lastval = i;
1605 pmc = 0;
1606 block_done = 1;
1607 }
1608 else {
1609 pmc = i;
1610 }
1611 } else if (abs(lc-clock/2) < tolerance) {
1612 // 32TO
1613 if((i - pmc) == lc) { /* 16T0 was previous one */
1614 /* It's a PMC ! */
1615 i += (128+127+16+32+33)-1;
1616 lastval = i;
1617 pmc = 0;
1618 block_done = 1;
1619 }
1620 else if(half_switch == 1) {
1621 bits[bitidx++] = 0;
1622 half_switch = 0;
1623 }
1624 else
1625 half_switch++;
1626 } else if (abs(lc-clock) < tolerance) {
1627 // 64TO
1628 bits[bitidx++] = 1;
1629 } else {
1630 // Error
1631 warnings++;
1632 if (warnings > 10)
1633 {
1634 Dbprintf("Error: too many detection errors, aborting.");
1635 return 0;
1636 }
1637 }
1638
1639 if(block_done == 1) {
1640 if(bitidx == 128) {
1641 for(j=0; j<16; j++) {
1642 blocks[num_blocks][j] = 128*bits[j*8+7]+
1643 64*bits[j*8+6]+
1644 32*bits[j*8+5]+
1645 16*bits[j*8+4]+
1646 8*bits[j*8+3]+
1647 4*bits[j*8+2]+
1648 2*bits[j*8+1]+
1649 bits[j*8];
1650
1651 }
1652 num_blocks++;
1653 }
1654 bitidx = 0;
1655 block_done = 0;
1656 half_switch = 0;
1657 }
1658 if(i < GraphTraceLen)
1659 dir =(dest[i-1] > dest[i]) ? 0 : 1;
1660 }
1661 if(bitidx==255)
1662 bitidx=0;
1663 warnings = 0;
1664 if(num_blocks == 4) break;
1665 }
1666 memcpy(outBlocks, blocks, 16*num_blocks);
1667 return num_blocks;
1668 }
1669
1670 int IsBlock0PCF7931(uint8_t *Block) {
1671 // Assume RFU means 0 :)
1672 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1673 return 1;
1674 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1675 return 1;
1676 return 0;
1677 }
1678
1679 int IsBlock1PCF7931(uint8_t *Block) {
1680 // Assume RFU means 0 :)
1681 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1682 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1683 return 1;
1684
1685 return 0;
1686 }
1687
1688 #define ALLOC 16
1689
1690 void ReadPCF7931() {
1691 uint8_t Blocks[8][17];
1692 uint8_t tmpBlocks[4][16];
1693 int i, j, ind, ind2, n;
1694 int num_blocks = 0;
1695 int max_blocks = 8;
1696 int ident = 0;
1697 int error = 0;
1698 int tries = 0;
1699
1700 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1701
1702 do {
1703 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1704 n = DemodPCF7931((uint8_t**)tmpBlocks);
1705 if(!n)
1706 error++;
1707 if(error==10 && num_blocks == 0) {
1708 Dbprintf("Error, no tag or bad tag");
1709 return;
1710 }
1711 else if (tries==20 || error==10) {
1712 Dbprintf("Error reading the tag");
1713 Dbprintf("Here is the partial content");
1714 goto end;
1715 }
1716
1717 for(i=0; i<n; i++)
1718 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1719 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1720 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1721 if(!ident) {
1722 for(i=0; i<n; i++) {
1723 if(IsBlock0PCF7931(tmpBlocks[i])) {
1724 // Found block 0 ?
1725 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1726 // Found block 1!
1727 // \o/
1728 ident = 1;
1729 memcpy(Blocks[0], tmpBlocks[i], 16);
1730 Blocks[0][ALLOC] = 1;
1731 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1732 Blocks[1][ALLOC] = 1;
1733 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1734 // Debug print
1735 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1736 num_blocks = 2;
1737 // Handle following blocks
1738 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1739 if(j==n) j=0;
1740 if(j==i) break;
1741 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1742 Blocks[ind2][ALLOC] = 1;
1743 }
1744 break;
1745 }
1746 }
1747 }
1748 }
1749 else {
1750 for(i=0; i<n; i++) { // Look for identical block in known blocks
1751 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1752 for(j=0; j<max_blocks; j++) {
1753 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1754 // Found an identical block
1755 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1756 if(ind2 < 0)
1757 ind2 = max_blocks;
1758 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1759 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1760 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1761 Blocks[ind2][ALLOC] = 1;
1762 num_blocks++;
1763 if(num_blocks == max_blocks) goto end;
1764 }
1765 }
1766 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1767 if(ind2 > max_blocks)
1768 ind2 = 0;
1769 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1770 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1771 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1772 Blocks[ind2][ALLOC] = 1;
1773 num_blocks++;
1774 if(num_blocks == max_blocks) goto end;
1775 }
1776 }
1777 }
1778 }
1779 }
1780 }
1781 }
1782 tries++;
1783 if (BUTTON_PRESS()) return;
1784 } while (num_blocks != max_blocks);
1785 end:
1786 Dbprintf("-----------------------------------------");
1787 Dbprintf("Memory content:");
1788 Dbprintf("-----------------------------------------");
1789 for(i=0; i<max_blocks; i++) {
1790 if(Blocks[i][ALLOC]==1)
1791 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1792 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1793 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1794 else
1795 Dbprintf("<missing block %d>", i);
1796 }
1797 Dbprintf("-----------------------------------------");
1798
1799 return ;
1800 }
1801
1802
1803 //-----------------------------------
1804 // EM4469 / EM4305 routines
1805 //-----------------------------------
1806 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1807 #define FWD_CMD_WRITE 0xA
1808 #define FWD_CMD_READ 0x9
1809 #define FWD_CMD_DISABLE 0x5
1810
1811
1812 uint8_t forwardLink_data[64]; //array of forwarded bits
1813 uint8_t * forward_ptr; //ptr for forward message preparation
1814 uint8_t fwd_bit_sz; //forwardlink bit counter
1815 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1816
1817 //====================================================================
1818 // prepares command bits
1819 // see EM4469 spec
1820 //====================================================================
1821 //--------------------------------------------------------------------
1822 uint8_t Prepare_Cmd( uint8_t cmd ) {
1823 //--------------------------------------------------------------------
1824
1825 *forward_ptr++ = 0; //start bit
1826 *forward_ptr++ = 0; //second pause for 4050 code
1827
1828 *forward_ptr++ = cmd;
1829 cmd >>= 1;
1830 *forward_ptr++ = cmd;
1831 cmd >>= 1;
1832 *forward_ptr++ = cmd;
1833 cmd >>= 1;
1834 *forward_ptr++ = cmd;
1835
1836 return 6; //return number of emited bits
1837 }
1838
1839 //====================================================================
1840 // prepares address bits
1841 // see EM4469 spec
1842 //====================================================================
1843
1844 //--------------------------------------------------------------------
1845 uint8_t Prepare_Addr( uint8_t addr ) {
1846 //--------------------------------------------------------------------
1847
1848 register uint8_t line_parity;
1849
1850 uint8_t i;
1851 line_parity = 0;
1852 for(i=0;i<6;i++) {
1853 *forward_ptr++ = addr;
1854 line_parity ^= addr;
1855 addr >>= 1;
1856 }
1857
1858 *forward_ptr++ = (line_parity & 1);
1859
1860 return 7; //return number of emited bits
1861 }
1862
1863 //====================================================================
1864 // prepares data bits intreleaved with parity bits
1865 // see EM4469 spec
1866 //====================================================================
1867
1868 //--------------------------------------------------------------------
1869 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1870 //--------------------------------------------------------------------
1871
1872 register uint8_t line_parity;
1873 register uint8_t column_parity;
1874 register uint8_t i, j;
1875 register uint16_t data;
1876
1877 data = data_low;
1878 column_parity = 0;
1879
1880 for(i=0; i<4; i++) {
1881 line_parity = 0;
1882 for(j=0; j<8; j++) {
1883 line_parity ^= data;
1884 column_parity ^= (data & 1) << j;
1885 *forward_ptr++ = data;
1886 data >>= 1;
1887 }
1888 *forward_ptr++ = line_parity;
1889 if(i == 1)
1890 data = data_hi;
1891 }
1892
1893 for(j=0; j<8; j++) {
1894 *forward_ptr++ = column_parity;
1895 column_parity >>= 1;
1896 }
1897 *forward_ptr = 0;
1898
1899 return 45; //return number of emited bits
1900 }
1901
1902 //====================================================================
1903 // Forward Link send function
1904 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1905 // fwd_bit_count set with number of bits to be sent
1906 //====================================================================
1907 void SendForward(uint8_t fwd_bit_count) {
1908
1909 fwd_write_ptr = forwardLink_data;
1910 fwd_bit_sz = fwd_bit_count;
1911
1912 LED_D_ON();
1913
1914 //Field on
1915 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1916 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1917 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1918
1919 // Give it a bit of time for the resonant antenna to settle.
1920 // And for the tag to fully power up
1921 SpinDelay(150);
1922
1923 // force 1st mod pulse (start gap must be longer for 4305)
1924 fwd_bit_sz--; //prepare next bit modulation
1925 fwd_write_ptr++;
1926 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1927 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1928 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1929 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1930 SpinDelayUs(16*8); //16 cycles on (8us each)
1931
1932 // now start writting
1933 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1934 if(((*fwd_write_ptr++) & 1) == 1)
1935 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1936 else {
1937 //These timings work for 4469/4269/4305 (with the 55*8 above)
1938 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1939 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1940 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1941 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1942 SpinDelayUs(9*8); //16 cycles on (8us each)
1943 }
1944 }
1945 }
1946
1947 void EM4xLogin(uint32_t Password) {
1948
1949 uint8_t fwd_bit_count;
1950
1951 forward_ptr = forwardLink_data;
1952 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1953 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1954
1955 SendForward(fwd_bit_count);
1956
1957 //Wait for command to complete
1958 SpinDelay(20);
1959
1960 }
1961
1962 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1963
1964 uint8_t *dest = BigBuf_get_addr();
1965 uint16_t bufferlength = BigBuf_max_traceLen();
1966 uint32_t i = 0;
1967
1968 // Clear destination buffer before sending the command 0x80 = average.
1969 memset(dest, 0x80, bufferlength);
1970
1971 uint8_t fwd_bit_count;
1972
1973 //If password mode do login
1974 if (PwdMode == 1) EM4xLogin(Pwd);
1975
1976 forward_ptr = forwardLink_data;
1977 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1978 fwd_bit_count += Prepare_Addr( Address );
1979
1980 // Connect the A/D to the peak-detected low-frequency path.
1981 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1982 // Now set up the SSC to get the ADC samples that are now streaming at us.
1983 FpgaSetupSsc();
1984
1985 SendForward(fwd_bit_count);
1986
1987 // Now do the acquisition
1988 i = 0;
1989 for(;;) {
1990 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1991 AT91C_BASE_SSC->SSC_THR = 0x43;
1992 }
1993 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1994 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1995 ++i;
1996 if (i >= bufferlength) break;
1997 }
1998 }
1999
2000 cmd_send(CMD_ACK,0,0,0,0,0);
2001 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2002 LED_D_OFF();
2003 }
2004
2005 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2006
2007 uint8_t fwd_bit_count;
2008
2009 //If password mode do login
2010 if (PwdMode == 1) EM4xLogin(Pwd);
2011
2012 forward_ptr = forwardLink_data;
2013 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2014 fwd_bit_count += Prepare_Addr( Address );
2015 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2016
2017 SendForward(fwd_bit_count);
2018
2019 //Wait for write to complete
2020 SpinDelay(20);
2021 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2022 LED_D_OFF();
2023 }
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