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Merge pull request #165 from wllm-rbnt/master
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 static uint32_t iso14a_timeout;
25 int rsamples = 0;
26 uint8_t trigger = 0;
27 // the block number for the ISO14443-4 PCB
28 static uint8_t iso14_pcb_blocknum = 0;
29
30 //
31 // ISO14443 timing:
32 //
33 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34 #define REQUEST_GUARD_TIME (7000/16 + 1)
35 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37 // bool LastCommandWasRequest = FALSE;
38
39 //
40 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41 //
42 // When the PM acts as reader and is receiving tag data, it takes
43 // 3 ticks delay in the AD converter
44 // 16 ticks until the modulation detector completes and sets curbit
45 // 8 ticks until bit_to_arm is assigned from curbit
46 // 8*16 ticks for the transfer from FPGA to ARM
47 // 4*16 ticks until we measure the time
48 // - 8*16 ticks because we measure the time of the previous transfer
49 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
50
51 // When the PM acts as a reader and is sending, it takes
52 // 4*16 ticks until we can write data to the sending hold register
53 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
54 // 8 ticks until the first transfer starts
55 // 8 ticks later the FPGA samples the data
56 // 1 tick to assign mod_sig_coil
57 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59 // When the PM acts as tag and is receiving it takes
60 // 2 ticks delay in the RF part (for the first falling edge),
61 // 3 ticks for the A/D conversion,
62 // 8 ticks on average until the start of the SSC transfer,
63 // 8 ticks until the SSC samples the first data
64 // 7*16 ticks to complete the transfer from FPGA to ARM
65 // 8 ticks until the next ssp_clk rising edge
66 // 4*16 ticks until we measure the time
67 // - 8*16 ticks because we measure the time of the previous transfer
68 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
69
70 // The FPGA will report its internal sending delay in
71 uint16_t FpgaSendQueueDelay;
72 // the 5 first bits are the number of bits buffered in mod_sig_buf
73 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76 // When the PM acts as tag and is sending, it takes
77 // 4*16 ticks until we can write data to the sending hold register
78 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
79 // 8 ticks until the first transfer starts
80 // 8 ticks later the FPGA samples the data
81 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82 // + 1 tick to assign mod_sig_coil
83 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
84
85 // When the PM acts as sniffer and is receiving tag data, it takes
86 // 3 ticks A/D conversion
87 // 14 ticks to complete the modulation detection
88 // 8 ticks (on average) until the result is stored in to_arm
89 // + the delays in transferring data - which is the same for
90 // sniffing reader and tag data and therefore not relevant
91 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
92
93 // When the PM acts as sniffer and is receiving reader data, it takes
94 // 2 ticks delay in analogue RF receiver (for the falling edge of the
95 // start bit, which marks the start of the communication)
96 // 3 ticks A/D conversion
97 // 8 ticks on average until the data is stored in to_arm.
98 // + the delays in transferring data - which is the same for
99 // sniffing reader and tag data and therefore not relevant
100 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
101
102 //variables used for timing purposes:
103 //these are in ssp_clk cycles:
104 static uint32_t NextTransferTime;
105 static uint32_t LastTimeProxToAirStart;
106 static uint32_t LastProxToAirDuration;
107
108
109
110 // CARD TO READER - manchester
111 // Sequence D: 11110000 modulation with subcarrier during first half
112 // Sequence E: 00001111 modulation with subcarrier during second half
113 // Sequence F: 00000000 no modulation with subcarrier
114 // READER TO CARD - miller
115 // Sequence X: 00001100 drop after half a period
116 // Sequence Y: 00000000 no drop
117 // Sequence Z: 11000000 drop at start
118 #define SEC_D 0xf0
119 #define SEC_E 0x0f
120 #define SEC_F 0x00
121 #define SEC_X 0x0c
122 #define SEC_Y 0x00
123 #define SEC_Z 0xc0
124
125 const uint8_t OddByteParity[256] = {
126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142 };
143
144
145 void iso14a_set_trigger(bool enable) {
146 trigger = enable;
147 }
148
149
150 void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
152 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
153 }
154
155
156 void iso14a_set_ATS_timeout(uint8_t *ats) {
157
158 uint8_t tb1;
159 uint8_t fwi;
160 uint32_t fwt;
161
162 if (ats[0] > 1) { // there is a format byte T0
163 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
165 tb1 = ats[3];
166 } else {
167 tb1 = ats[2];
168 }
169 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
171
172 iso14a_set_timeout(fwt/(8*16));
173 }
174 }
175 }
176
177
178 //-----------------------------------------------------------------------------
179 // Generate the parity value for a byte sequence
180 //
181 //-----------------------------------------------------------------------------
182 byte_t oddparity (const byte_t bt)
183 {
184 return OddByteParity[bt];
185 }
186
187 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
188 {
189 uint16_t paritybit_cnt = 0;
190 uint16_t paritybyte_cnt = 0;
191 uint8_t parityBits = 0;
192
193 for (uint16_t i = 0; i < iLen; i++) {
194 // Generate the parity bits
195 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
196 if (paritybit_cnt == 7) {
197 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
198 parityBits = 0; // and advance to next Parity Byte
199 paritybyte_cnt++;
200 paritybit_cnt = 0;
201 } else {
202 paritybit_cnt++;
203 }
204 }
205
206 // save remaining parity bits
207 par[paritybyte_cnt] = parityBits;
208
209 }
210
211 void AppendCrc14443a(uint8_t* data, int len)
212 {
213 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
214 }
215
216 void AppendCrc14443b(uint8_t* data, int len)
217 {
218 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
219 }
220
221
222 //=============================================================================
223 // ISO 14443 Type A - Miller decoder
224 //=============================================================================
225 // Basics:
226 // This decoder is used when the PM3 acts as a tag.
227 // The reader will generate "pauses" by temporarily switching of the field.
228 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
229 // The FPGA does a comparison with a threshold and would deliver e.g.:
230 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
231 // The Miller decoder needs to identify the following sequences:
232 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
233 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
234 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
235 // Note 1: the bitstream may start at any time. We therefore need to sync.
236 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
237 //-----------------------------------------------------------------------------
238 static tUart Uart;
239
240 // Lookup-Table to decide if 4 raw bits are a modulation.
241 // We accept the following:
242 // 0001 - a 3 tick wide pause
243 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
244 // 0111 - a 2 tick wide pause shifted left
245 // 1001 - a 2 tick wide pause shifted right
246 const bool Mod_Miller_LUT[] = {
247 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
248 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
249 };
250 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
251 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
252
253 void UartReset()
254 {
255 Uart.state = STATE_UNSYNCD;
256 Uart.bitCount = 0;
257 Uart.len = 0; // number of decoded data bytes
258 Uart.parityLen = 0; // number of decoded parity bytes
259 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
260 Uart.parityBits = 0; // holds 8 parity bits
261 Uart.startTime = 0;
262 Uart.endTime = 0;
263 }
264
265 void UartInit(uint8_t *data, uint8_t *parity)
266 {
267 Uart.output = data;
268 Uart.parity = parity;
269 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
270 UartReset();
271 }
272
273 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
274 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
275 {
276
277 Uart.fourBits = (Uart.fourBits << 8) | bit;
278
279 if (Uart.state == STATE_UNSYNCD) { // not yet synced
280
281 Uart.syncBit = 9999; // not set
282 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
283 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
284 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
285 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
286 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
287 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
288 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
289 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
290 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
291 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
292 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
293 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
294 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
295 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
296
297 if (Uart.syncBit != 9999) { // found a sync bit
298 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
299 Uart.startTime -= Uart.syncBit;
300 Uart.endTime = Uart.startTime;
301 Uart.state = STATE_START_OF_COMMUNICATION;
302 }
303
304 } else {
305
306 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
307 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
308 UartReset();
309 } else { // Modulation in first half = Sequence Z = logic "0"
310 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
311 UartReset();
312 } else {
313 Uart.bitCount++;
314 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
315 Uart.state = STATE_MILLER_Z;
316 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
317 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
318 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
319 Uart.parityBits <<= 1; // make room for the parity bit
320 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
321 Uart.bitCount = 0;
322 Uart.shiftReg = 0;
323 if((Uart.len&0x0007) == 0) { // every 8 data bytes
324 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
325 Uart.parityBits = 0;
326 }
327 }
328 }
329 }
330 } else {
331 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
334 Uart.state = STATE_MILLER_X;
335 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
336 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
337 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
338 Uart.parityBits <<= 1; // make room for the new parity bit
339 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
340 Uart.bitCount = 0;
341 Uart.shiftReg = 0;
342 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
343 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
344 Uart.parityBits = 0;
345 }
346 }
347 } else { // no modulation in both halves - Sequence Y
348 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
349 Uart.state = STATE_UNSYNCD;
350 Uart.bitCount--; // last "0" was part of EOC sequence
351 Uart.shiftReg <<= 1; // drop it
352 if(Uart.bitCount > 0) { // if we decoded some bits
353 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
354 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
355 Uart.parityBits <<= 1; // add a (void) parity bit
356 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
357 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
358 return TRUE;
359 } else if (Uart.len & 0x0007) { // there are some parity bits to store
360 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
361 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
362 }
363 if (Uart.len) {
364 return TRUE; // we are finished with decoding the raw data sequence
365 } else {
366 UartReset(); // Nothing received - start over
367 }
368 }
369 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
370 UartReset();
371 } else { // a logic "0"
372 Uart.bitCount++;
373 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
374 Uart.state = STATE_MILLER_Y;
375 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
376 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
377 Uart.parityBits <<= 1; // make room for the parity bit
378 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
379 Uart.bitCount = 0;
380 Uart.shiftReg = 0;
381 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
382 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
383 Uart.parityBits = 0;
384 }
385 }
386 }
387 }
388 }
389
390 }
391
392 return FALSE; // not finished yet, need more data
393 }
394
395
396
397 //=============================================================================
398 // ISO 14443 Type A - Manchester decoder
399 //=============================================================================
400 // Basics:
401 // This decoder is used when the PM3 acts as a reader.
402 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
403 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
404 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
405 // The Manchester decoder needs to identify the following sequences:
406 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
407 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
408 // 8 ticks unmodulated: Sequence F = end of communication
409 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
410 // Note 1: the bitstream may start at any time. We therefore need to sync.
411 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
412 static tDemod Demod;
413
414 // Lookup-Table to decide if 4 raw bits are a modulation.
415 // We accept three or four "1" in any position
416 const bool Mod_Manchester_LUT[] = {
417 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
418 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
419 };
420
421 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
422 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
423
424
425 void DemodReset()
426 {
427 Demod.state = DEMOD_UNSYNCD;
428 Demod.len = 0; // number of decoded data bytes
429 Demod.parityLen = 0;
430 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
431 Demod.parityBits = 0; //
432 Demod.collisionPos = 0; // Position of collision bit
433 Demod.twoBits = 0xffff; // buffer for 2 Bits
434 Demod.highCnt = 0;
435 Demod.startTime = 0;
436 Demod.endTime = 0;
437 }
438
439 void DemodInit(uint8_t *data, uint8_t *parity)
440 {
441 Demod.output = data;
442 Demod.parity = parity;
443 DemodReset();
444 }
445
446 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
447 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
448 {
449
450 Demod.twoBits = (Demod.twoBits << 8) | bit;
451
452 if (Demod.state == DEMOD_UNSYNCD) {
453
454 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
455 if (Demod.twoBits == 0x0000) {
456 Demod.highCnt++;
457 } else {
458 Demod.highCnt = 0;
459 }
460 } else {
461 Demod.syncBit = 0xFFFF; // not set
462 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
463 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
464 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
465 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
466 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
467 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
468 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
469 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
470 if (Demod.syncBit != 0xFFFF) {
471 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
472 Demod.startTime -= Demod.syncBit;
473 Demod.bitCount = offset; // number of decoded data bits
474 Demod.state = DEMOD_MANCHESTER_DATA;
475 }
476 }
477
478 } else {
479
480 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
481 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
482 if (!Demod.collisionPos) {
483 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
484 }
485 } // modulation in first half only - Sequence D = 1
486 Demod.bitCount++;
487 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
488 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
489 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
490 Demod.parityBits <<= 1; // make room for the parity bit
491 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
492 Demod.bitCount = 0;
493 Demod.shiftReg = 0;
494 if((Demod.len&0x0007) == 0) { // every 8 data bytes
495 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
496 Demod.parityBits = 0;
497 }
498 }
499 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
500 } else { // no modulation in first half
501 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
502 Demod.bitCount++;
503 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
504 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
505 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
506 Demod.parityBits <<= 1; // make room for the new parity bit
507 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
508 Demod.bitCount = 0;
509 Demod.shiftReg = 0;
510 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
511 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
512 Demod.parityBits = 0;
513 }
514 }
515 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
516 } else { // no modulation in both halves - End of communication
517 if(Demod.bitCount > 0) { // there are some remaining data bits
518 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
519 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
520 Demod.parityBits <<= 1; // add a (void) parity bit
521 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
522 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
523 return TRUE;
524 } else if (Demod.len & 0x0007) { // there are some parity bits to store
525 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
526 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
527 }
528 if (Demod.len) {
529 return TRUE; // we are finished with decoding the raw data sequence
530 } else { // nothing received. Start over
531 DemodReset();
532 }
533 }
534 }
535
536 }
537
538 return FALSE; // not finished yet, need more data
539 }
540
541 //=============================================================================
542 // Finally, a `sniffer' for ISO 14443 Type A
543 // Both sides of communication!
544 //=============================================================================
545
546 //-----------------------------------------------------------------------------
547 // Record the sequence of commands sent by the reader to the tag, with
548 // triggering so that we start recording at the point that the tag is moved
549 // near the reader.
550 //-----------------------------------------------------------------------------
551 void RAMFUNC SnoopIso14443a(uint8_t param) {
552 // param:
553 // bit 0 - trigger from first card answer
554 // bit 1 - trigger from first reader 7-bit request
555
556 LEDsoff();
557
558 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
559
560 // Allocate memory from BigBuf for some buffers
561 // free all previous allocations first
562 BigBuf_free();
563
564 // The command (reader -> tag) that we're receiving.
565 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
566 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
567
568 // The response (tag -> reader) that we're receiving.
569 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
570 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
571
572 // The DMA buffer, used to stream samples from the FPGA
573 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
574
575 // init trace buffer
576 clear_trace();
577 set_tracing(TRUE);
578
579 uint8_t *data = dmaBuf;
580 uint8_t previous_data = 0;
581 int maxDataLen = 0;
582 int dataLen = 0;
583 bool TagIsActive = FALSE;
584 bool ReaderIsActive = FALSE;
585
586 // Set up the demodulator for tag -> reader responses.
587 DemodInit(receivedResponse, receivedResponsePar);
588
589 // Set up the demodulator for the reader -> tag commands
590 UartInit(receivedCmd, receivedCmdPar);
591
592 // Setup and start DMA.
593 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
594
595 // We won't start recording the frames that we acquire until we trigger;
596 // a good trigger condition to get started is probably when we see a
597 // response from the tag.
598 // triggered == FALSE -- to wait first for card
599 bool triggered = !(param & 0x03);
600
601 // And now we loop, receiving samples.
602 for(uint32_t rsamples = 0; TRUE; ) {
603
604 if(BUTTON_PRESS()) {
605 DbpString("cancelled by button");
606 break;
607 }
608
609 LED_A_ON();
610 WDT_HIT();
611
612 int register readBufDataP = data - dmaBuf;
613 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
614 if (readBufDataP <= dmaBufDataP){
615 dataLen = dmaBufDataP - readBufDataP;
616 } else {
617 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
618 }
619 // test for length of buffer
620 if(dataLen > maxDataLen) {
621 maxDataLen = dataLen;
622 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
623 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
624 break;
625 }
626 }
627 if(dataLen < 1) continue;
628
629 // primary buffer was stopped( <-- we lost data!
630 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
631 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
632 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
633 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
634 }
635 // secondary buffer sets as primary, secondary buffer was stopped
636 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
637 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
638 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
639 }
640
641 LED_A_OFF();
642
643 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
644
645 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
646 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
647 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
648 LED_C_ON();
649
650 // check - if there is a short 7bit request from reader
651 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
652
653 if(triggered) {
654 if (!LogTrace(receivedCmd,
655 Uart.len,
656 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
657 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
658 Uart.parity,
659 TRUE)) break;
660 }
661 /* And ready to receive another command. */
662 UartReset();
663 /* And also reset the demod code, which might have been */
664 /* false-triggered by the commands from the reader. */
665 DemodReset();
666 LED_B_OFF();
667 }
668 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
669 }
670
671 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
672 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
673 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
674 LED_B_ON();
675
676 if (!LogTrace(receivedResponse,
677 Demod.len,
678 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
679 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
680 Demod.parity,
681 FALSE)) break;
682
683 if ((!triggered) && (param & 0x01)) triggered = TRUE;
684
685 // And ready to receive another response.
686 DemodReset();
687 // And reset the Miller decoder including itS (now outdated) input buffer
688 UartInit(receivedCmd, receivedCmdPar);
689
690 LED_C_OFF();
691 }
692 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
693 }
694 }
695
696 previous_data = *data;
697 rsamples++;
698 data++;
699 if(data == dmaBuf + DMA_BUFFER_SIZE) {
700 data = dmaBuf;
701 }
702 } // main cycle
703
704 DbpString("COMMAND FINISHED");
705
706 FpgaDisableSscDma();
707 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
708 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
709 LEDsoff();
710 }
711
712 //-----------------------------------------------------------------------------
713 // Prepare tag messages
714 //-----------------------------------------------------------------------------
715 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
716 {
717 ToSendReset();
718
719 // Correction bit, might be removed when not needed
720 ToSendStuffBit(0);
721 ToSendStuffBit(0);
722 ToSendStuffBit(0);
723 ToSendStuffBit(0);
724 ToSendStuffBit(1); // 1
725 ToSendStuffBit(0);
726 ToSendStuffBit(0);
727 ToSendStuffBit(0);
728
729 // Send startbit
730 ToSend[++ToSendMax] = SEC_D;
731 LastProxToAirDuration = 8 * ToSendMax - 4;
732
733 for(uint16_t i = 0; i < len; i++) {
734 uint8_t b = cmd[i];
735
736 // Data bits
737 for(uint16_t j = 0; j < 8; j++) {
738 if(b & 1) {
739 ToSend[++ToSendMax] = SEC_D;
740 } else {
741 ToSend[++ToSendMax] = SEC_E;
742 }
743 b >>= 1;
744 }
745
746 // Get the parity bit
747 if (parity[i>>3] & (0x80>>(i&0x0007))) {
748 ToSend[++ToSendMax] = SEC_D;
749 LastProxToAirDuration = 8 * ToSendMax - 4;
750 } else {
751 ToSend[++ToSendMax] = SEC_E;
752 LastProxToAirDuration = 8 * ToSendMax;
753 }
754 }
755
756 // Send stopbit
757 ToSend[++ToSendMax] = SEC_F;
758
759 // Convert from last byte pos to length
760 ToSendMax++;
761 }
762
763 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
764 {
765 uint8_t par[MAX_PARITY_SIZE];
766
767 GetParity(cmd, len, par);
768 CodeIso14443aAsTagPar(cmd, len, par);
769 }
770
771
772 static void Code4bitAnswerAsTag(uint8_t cmd)
773 {
774 int i;
775
776 ToSendReset();
777
778 // Correction bit, might be removed when not needed
779 ToSendStuffBit(0);
780 ToSendStuffBit(0);
781 ToSendStuffBit(0);
782 ToSendStuffBit(0);
783 ToSendStuffBit(1); // 1
784 ToSendStuffBit(0);
785 ToSendStuffBit(0);
786 ToSendStuffBit(0);
787
788 // Send startbit
789 ToSend[++ToSendMax] = SEC_D;
790
791 uint8_t b = cmd;
792 for(i = 0; i < 4; i++) {
793 if(b & 1) {
794 ToSend[++ToSendMax] = SEC_D;
795 LastProxToAirDuration = 8 * ToSendMax - 4;
796 } else {
797 ToSend[++ToSendMax] = SEC_E;
798 LastProxToAirDuration = 8 * ToSendMax;
799 }
800 b >>= 1;
801 }
802
803 // Send stopbit
804 ToSend[++ToSendMax] = SEC_F;
805
806 // Convert from last byte pos to length
807 ToSendMax++;
808 }
809
810 //-----------------------------------------------------------------------------
811 // Wait for commands from reader
812 // Stop when button is pressed
813 // Or return TRUE when command is captured
814 //-----------------------------------------------------------------------------
815 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
816 {
817 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
818 // only, since we are receiving, not transmitting).
819 // Signal field is off with the appropriate LED
820 LED_D_OFF();
821 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
822
823 // Now run a `software UART' on the stream of incoming samples.
824 UartInit(received, parity);
825
826 // clear RXRDY:
827 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
828
829 for(;;) {
830 WDT_HIT();
831
832 if(BUTTON_PRESS()) return FALSE;
833
834 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
835 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
836 if(MillerDecoding(b, 0)) {
837 *len = Uart.len;
838 return TRUE;
839 }
840 }
841 }
842 }
843
844 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
845 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
846 int EmSend4bit(uint8_t resp);
847 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
848 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
849 int EmSendCmd(uint8_t *resp, uint16_t respLen);
850 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
851 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
852 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
853
854 static uint8_t* free_buffer_pointer;
855
856 typedef struct {
857 uint8_t* response;
858 size_t response_n;
859 uint8_t* modulation;
860 size_t modulation_n;
861 uint32_t ProxToAirDuration;
862 } tag_response_info_t;
863
864 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
865 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
866 // This will need the following byte array for a modulation sequence
867 // 144 data bits (18 * 8)
868 // 18 parity bits
869 // 2 Start and stop
870 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
871 // 1 just for the case
872 // ----------- +
873 // 166 bytes, since every bit that needs to be send costs us a byte
874 //
875
876
877 // Prepare the tag modulation bits from the message
878 CodeIso14443aAsTag(response_info->response,response_info->response_n);
879
880 // Make sure we do not exceed the free buffer space
881 if (ToSendMax > max_buffer_size) {
882 Dbprintf("Out of memory, when modulating bits for tag answer:");
883 Dbhexdump(response_info->response_n,response_info->response,false);
884 return false;
885 }
886
887 // Copy the byte array, used for this modulation to the buffer position
888 memcpy(response_info->modulation,ToSend,ToSendMax);
889
890 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
891 response_info->modulation_n = ToSendMax;
892 response_info->ProxToAirDuration = LastProxToAirDuration;
893
894 return true;
895 }
896
897
898 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
899 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
900 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
901 // -> need 273 bytes buffer
902 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
903
904 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
905 // Retrieve and store the current buffer index
906 response_info->modulation = free_buffer_pointer;
907
908 // Determine the maximum size we can use from our buffer
909 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
910
911 // Forward the prepare tag modulation function to the inner function
912 if (prepare_tag_modulation(response_info, max_buffer_size)) {
913 // Update the free buffer offset
914 free_buffer_pointer += ToSendMax;
915 return true;
916 } else {
917 return false;
918 }
919 }
920
921 //-----------------------------------------------------------------------------
922 // Main loop of simulated tag: receive commands from reader, decide what
923 // response to send, and send it.
924 //-----------------------------------------------------------------------------
925 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
926 {
927 uint8_t sak;
928
929 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
930 uint8_t response1[2];
931
932 switch (tagType) {
933 case 1: { // MIFARE Classic
934 // Says: I am Mifare 1k - original line
935 response1[0] = 0x04;
936 response1[1] = 0x00;
937 sak = 0x08;
938 } break;
939 case 2: { // MIFARE Ultralight
940 // Says: I am a stupid memory tag, no crypto
941 response1[0] = 0x04;
942 response1[1] = 0x00;
943 sak = 0x00;
944 } break;
945 case 3: { // MIFARE DESFire
946 // Says: I am a DESFire tag, ph33r me
947 response1[0] = 0x04;
948 response1[1] = 0x03;
949 sak = 0x20;
950 } break;
951 case 4: { // ISO/IEC 14443-4
952 // Says: I am a javacard (JCOP)
953 response1[0] = 0x04;
954 response1[1] = 0x00;
955 sak = 0x28;
956 } break;
957 case 5: { // MIFARE TNP3XXX
958 // Says: I am a toy
959 response1[0] = 0x01;
960 response1[1] = 0x0f;
961 sak = 0x01;
962 } break;
963 default: {
964 Dbprintf("Error: unkown tagtype (%d)",tagType);
965 return;
966 } break;
967 }
968
969 // The second response contains the (mandatory) first 24 bits of the UID
970 uint8_t response2[5] = {0x00};
971
972 // Check if the uid uses the (optional) part
973 uint8_t response2a[5] = {0x00};
974
975 if (uid_2nd) {
976 response2[0] = 0x88;
977 num_to_bytes(uid_1st,3,response2+1);
978 num_to_bytes(uid_2nd,4,response2a);
979 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
980
981 // Configure the ATQA and SAK accordingly
982 response1[0] |= 0x40;
983 sak |= 0x04;
984 } else {
985 num_to_bytes(uid_1st,4,response2);
986 // Configure the ATQA and SAK accordingly
987 response1[0] &= 0xBF;
988 sak &= 0xFB;
989 }
990
991 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
992 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
993
994 // Prepare the mandatory SAK (for 4 and 7 byte UID)
995 uint8_t response3[3] = {0x00};
996 response3[0] = sak;
997 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
998
999 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1000 uint8_t response3a[3] = {0x00};
1001 response3a[0] = sak & 0xFB;
1002 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1003
1004 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1005 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1006 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1007 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1008 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1009 // TC(1) = 0x02: CID supported, NAD not supported
1010 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1011
1012 #define TAG_RESPONSE_COUNT 7
1013 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1014 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1015 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1016 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1017 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1018 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1019 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1020 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1021 };
1022
1023 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1024 // Such a response is less time critical, so we can prepare them on the fly
1025 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1026 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1027 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1028 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1029 tag_response_info_t dynamic_response_info = {
1030 .response = dynamic_response_buffer,
1031 .response_n = 0,
1032 .modulation = dynamic_modulation_buffer,
1033 .modulation_n = 0
1034 };
1035
1036 // We need to listen to the high-frequency, peak-detected path.
1037 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1038
1039 BigBuf_free_keep_EM();
1040
1041 // allocate buffers:
1042 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1043 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1044 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1045
1046 // clear trace
1047 clear_trace();
1048 set_tracing(TRUE);
1049
1050 // Prepare the responses of the anticollision phase
1051 // there will be not enough time to do this at the moment the reader sends it REQA
1052 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1053 prepare_allocated_tag_modulation(&responses[i]);
1054 }
1055
1056 int len = 0;
1057
1058 // To control where we are in the protocol
1059 int order = 0;
1060 int lastorder;
1061
1062 // Just to allow some checks
1063 int happened = 0;
1064 int happened2 = 0;
1065 int cmdsRecvd = 0;
1066
1067 cmdsRecvd = 0;
1068 tag_response_info_t* p_response;
1069
1070 LED_A_ON();
1071 for(;;) {
1072 // Clean receive command buffer
1073 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1074 DbpString("Button press");
1075 break;
1076 }
1077
1078 p_response = NULL;
1079
1080 // Okay, look at the command now.
1081 lastorder = order;
1082 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1083 p_response = &responses[0]; order = 1;
1084 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1085 p_response = &responses[0]; order = 6;
1086 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1087 p_response = &responses[1]; order = 2;
1088 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1089 p_response = &responses[2]; order = 20;
1090 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1091 p_response = &responses[3]; order = 3;
1092 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1093 p_response = &responses[4]; order = 30;
1094 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1095 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1096 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1097 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1098 p_response = NULL;
1099 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1100
1101 if (tracing) {
1102 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1103 }
1104 p_response = NULL;
1105 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1106 p_response = &responses[5]; order = 7;
1107 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1108 if (tagType == 1 || tagType == 2) { // RATS not supported
1109 EmSend4bit(CARD_NACK_NA);
1110 p_response = NULL;
1111 } else {
1112 p_response = &responses[6]; order = 70;
1113 }
1114 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1115 if (tracing) {
1116 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1117 }
1118 uint32_t nr = bytes_to_num(receivedCmd,4);
1119 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1120 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1121 } else {
1122 // Check for ISO 14443A-4 compliant commands, look at left nibble
1123 switch (receivedCmd[0]) {
1124
1125 case 0x0B:
1126 case 0x0A: { // IBlock (command)
1127 dynamic_response_info.response[0] = receivedCmd[0];
1128 dynamic_response_info.response[1] = 0x00;
1129 dynamic_response_info.response[2] = 0x90;
1130 dynamic_response_info.response[3] = 0x00;
1131 dynamic_response_info.response_n = 4;
1132 } break;
1133
1134 case 0x1A:
1135 case 0x1B: { // Chaining command
1136 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1137 dynamic_response_info.response_n = 2;
1138 } break;
1139
1140 case 0xaa:
1141 case 0xbb: {
1142 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1143 dynamic_response_info.response_n = 2;
1144 } break;
1145
1146 case 0xBA: { //
1147 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1148 dynamic_response_info.response_n = 2;
1149 } break;
1150
1151 case 0xCA:
1152 case 0xC2: { // Readers sends deselect command
1153 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1154 dynamic_response_info.response_n = 2;
1155 } break;
1156
1157 default: {
1158 // Never seen this command before
1159 if (tracing) {
1160 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1161 }
1162 Dbprintf("Received unknown command (len=%d):",len);
1163 Dbhexdump(len,receivedCmd,false);
1164 // Do not respond
1165 dynamic_response_info.response_n = 0;
1166 } break;
1167 }
1168
1169 if (dynamic_response_info.response_n > 0) {
1170 // Copy the CID from the reader query
1171 dynamic_response_info.response[1] = receivedCmd[1];
1172
1173 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1174 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1175 dynamic_response_info.response_n += 2;
1176
1177 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1178 Dbprintf("Error preparing tag response");
1179 if (tracing) {
1180 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1181 }
1182 break;
1183 }
1184 p_response = &dynamic_response_info;
1185 }
1186 }
1187
1188 // Count number of wakeups received after a halt
1189 if(order == 6 && lastorder == 5) { happened++; }
1190
1191 // Count number of other messages after a halt
1192 if(order != 6 && lastorder == 5) { happened2++; }
1193
1194 if(cmdsRecvd > 999) {
1195 DbpString("1000 commands later...");
1196 break;
1197 }
1198 cmdsRecvd++;
1199
1200 if (p_response != NULL) {
1201 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1202 // do the tracing for the previous reader request and this tag answer:
1203 uint8_t par[MAX_PARITY_SIZE];
1204 GetParity(p_response->response, p_response->response_n, par);
1205
1206 EmLogTrace(Uart.output,
1207 Uart.len,
1208 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1209 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1210 Uart.parity,
1211 p_response->response,
1212 p_response->response_n,
1213 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1214 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1215 par);
1216 }
1217
1218 if (!tracing) {
1219 Dbprintf("Trace Full. Simulation stopped.");
1220 break;
1221 }
1222 }
1223
1224 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1225 LED_A_OFF();
1226 BigBuf_free_keep_EM();
1227 }
1228
1229
1230 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1231 // of bits specified in the delay parameter.
1232 void PrepareDelayedTransfer(uint16_t delay)
1233 {
1234 uint8_t bitmask = 0;
1235 uint8_t bits_to_shift = 0;
1236 uint8_t bits_shifted = 0;
1237
1238 delay &= 0x07;
1239 if (delay) {
1240 for (uint16_t i = 0; i < delay; i++) {
1241 bitmask |= (0x01 << i);
1242 }
1243 ToSend[ToSendMax++] = 0x00;
1244 for (uint16_t i = 0; i < ToSendMax; i++) {
1245 bits_to_shift = ToSend[i] & bitmask;
1246 ToSend[i] = ToSend[i] >> delay;
1247 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1248 bits_shifted = bits_to_shift;
1249 }
1250 }
1251 }
1252
1253
1254 //-------------------------------------------------------------------------------------
1255 // Transmit the command (to the tag) that was placed in ToSend[].
1256 // Parameter timing:
1257 // if NULL: transfer at next possible time, taking into account
1258 // request guard time and frame delay time
1259 // if == 0: transfer immediately and return time of transfer
1260 // if != 0: delay transfer until time specified
1261 //-------------------------------------------------------------------------------------
1262 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1263 {
1264
1265 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1266
1267 uint32_t ThisTransferTime = 0;
1268
1269 if (timing) {
1270 if(*timing == 0) { // Measure time
1271 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1272 } else {
1273 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1274 }
1275 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1276 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1277 LastTimeProxToAirStart = *timing;
1278 } else {
1279 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1280 while(GetCountSspClk() < ThisTransferTime);
1281 LastTimeProxToAirStart = ThisTransferTime;
1282 }
1283
1284 // clear TXRDY
1285 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1286
1287 uint16_t c = 0;
1288 for(;;) {
1289 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1290 AT91C_BASE_SSC->SSC_THR = cmd[c];
1291 c++;
1292 if(c >= len) {
1293 break;
1294 }
1295 }
1296 }
1297
1298 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1299 }
1300
1301
1302 //-----------------------------------------------------------------------------
1303 // Prepare reader command (in bits, support short frames) to send to FPGA
1304 //-----------------------------------------------------------------------------
1305 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1306 {
1307 int i, j;
1308 int last;
1309 uint8_t b;
1310
1311 ToSendReset();
1312
1313 // Start of Communication (Seq. Z)
1314 ToSend[++ToSendMax] = SEC_Z;
1315 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1316 last = 0;
1317
1318 size_t bytecount = nbytes(bits);
1319 // Generate send structure for the data bits
1320 for (i = 0; i < bytecount; i++) {
1321 // Get the current byte to send
1322 b = cmd[i];
1323 size_t bitsleft = MIN((bits-(i*8)),8);
1324
1325 for (j = 0; j < bitsleft; j++) {
1326 if (b & 1) {
1327 // Sequence X
1328 ToSend[++ToSendMax] = SEC_X;
1329 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1330 last = 1;
1331 } else {
1332 if (last == 0) {
1333 // Sequence Z
1334 ToSend[++ToSendMax] = SEC_Z;
1335 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1336 } else {
1337 // Sequence Y
1338 ToSend[++ToSendMax] = SEC_Y;
1339 last = 0;
1340 }
1341 }
1342 b >>= 1;
1343 }
1344
1345 // Only transmit parity bit if we transmitted a complete byte
1346 if (j == 8 && parity != NULL) {
1347 // Get the parity bit
1348 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1349 // Sequence X
1350 ToSend[++ToSendMax] = SEC_X;
1351 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1352 last = 1;
1353 } else {
1354 if (last == 0) {
1355 // Sequence Z
1356 ToSend[++ToSendMax] = SEC_Z;
1357 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1358 } else {
1359 // Sequence Y
1360 ToSend[++ToSendMax] = SEC_Y;
1361 last = 0;
1362 }
1363 }
1364 }
1365 }
1366
1367 // End of Communication: Logic 0 followed by Sequence Y
1368 if (last == 0) {
1369 // Sequence Z
1370 ToSend[++ToSendMax] = SEC_Z;
1371 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1372 } else {
1373 // Sequence Y
1374 ToSend[++ToSendMax] = SEC_Y;
1375 last = 0;
1376 }
1377 ToSend[++ToSendMax] = SEC_Y;
1378
1379 // Convert to length of command:
1380 ToSendMax++;
1381 }
1382
1383 //-----------------------------------------------------------------------------
1384 // Prepare reader command to send to FPGA
1385 //-----------------------------------------------------------------------------
1386 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1387 {
1388 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1389 }
1390
1391
1392 //-----------------------------------------------------------------------------
1393 // Wait for commands from reader
1394 // Stop when button is pressed (return 1) or field was gone (return 2)
1395 // Or return 0 when command is captured
1396 //-----------------------------------------------------------------------------
1397 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1398 {
1399 *len = 0;
1400
1401 uint32_t timer = 0, vtime = 0;
1402 int analogCnt = 0;
1403 int analogAVG = 0;
1404
1405 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1406 // only, since we are receiving, not transmitting).
1407 // Signal field is off with the appropriate LED
1408 LED_D_OFF();
1409 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1410
1411 // Set ADC to read field strength
1412 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1413 AT91C_BASE_ADC->ADC_MR =
1414 ADC_MODE_PRESCALE(63) |
1415 ADC_MODE_STARTUP_TIME(1) |
1416 ADC_MODE_SAMPLE_HOLD_TIME(15);
1417 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1418 // start ADC
1419 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1420
1421 // Now run a 'software UART' on the stream of incoming samples.
1422 UartInit(received, parity);
1423
1424 // Clear RXRDY:
1425 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1426
1427 for(;;) {
1428 WDT_HIT();
1429
1430 if (BUTTON_PRESS()) return 1;
1431
1432 // test if the field exists
1433 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1434 analogCnt++;
1435 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1436 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1437 if (analogCnt >= 32) {
1438 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1439 vtime = GetTickCount();
1440 if (!timer) timer = vtime;
1441 // 50ms no field --> card to idle state
1442 if (vtime - timer > 50) return 2;
1443 } else
1444 if (timer) timer = 0;
1445 analogCnt = 0;
1446 analogAVG = 0;
1447 }
1448 }
1449
1450 // receive and test the miller decoding
1451 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1452 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1453 if(MillerDecoding(b, 0)) {
1454 *len = Uart.len;
1455 return 0;
1456 }
1457 }
1458
1459 }
1460 }
1461
1462
1463 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1464 {
1465 uint8_t b;
1466 uint16_t i = 0;
1467 uint32_t ThisTransferTime;
1468
1469 // Modulate Manchester
1470 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1471
1472 // include correction bit if necessary
1473 if (Uart.parityBits & 0x01) {
1474 correctionNeeded = TRUE;
1475 }
1476 if(correctionNeeded) {
1477 // 1236, so correction bit needed
1478 i = 0;
1479 } else {
1480 i = 1;
1481 }
1482
1483 // clear receiving shift register and holding register
1484 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1485 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1486 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1487 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1488
1489 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1490 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1491 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1492 if (AT91C_BASE_SSC->SSC_RHR) break;
1493 }
1494
1495 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1496
1497 // Clear TXRDY:
1498 AT91C_BASE_SSC->SSC_THR = SEC_F;
1499
1500 // send cycle
1501 for(; i < respLen; ) {
1502 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1503 AT91C_BASE_SSC->SSC_THR = resp[i++];
1504 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1505 }
1506
1507 if(BUTTON_PRESS()) {
1508 break;
1509 }
1510 }
1511
1512 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1513 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1514 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1515 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1516 AT91C_BASE_SSC->SSC_THR = SEC_F;
1517 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1518 i++;
1519 }
1520 }
1521
1522 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1523
1524 return 0;
1525 }
1526
1527 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1528 Code4bitAnswerAsTag(resp);
1529 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1530 // do the tracing for the previous reader request and this tag answer:
1531 uint8_t par[1];
1532 GetParity(&resp, 1, par);
1533 EmLogTrace(Uart.output,
1534 Uart.len,
1535 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1536 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1537 Uart.parity,
1538 &resp,
1539 1,
1540 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1541 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1542 par);
1543 return res;
1544 }
1545
1546 int EmSend4bit(uint8_t resp){
1547 return EmSend4bitEx(resp, false);
1548 }
1549
1550 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1551 CodeIso14443aAsTagPar(resp, respLen, par);
1552 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1553 // do the tracing for the previous reader request and this tag answer:
1554 EmLogTrace(Uart.output,
1555 Uart.len,
1556 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1557 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1558 Uart.parity,
1559 resp,
1560 respLen,
1561 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1562 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1563 par);
1564 return res;
1565 }
1566
1567 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1568 uint8_t par[MAX_PARITY_SIZE];
1569 GetParity(resp, respLen, par);
1570 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1571 }
1572
1573 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1574 uint8_t par[MAX_PARITY_SIZE];
1575 GetParity(resp, respLen, par);
1576 return EmSendCmdExPar(resp, respLen, false, par);
1577 }
1578
1579 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1580 return EmSendCmdExPar(resp, respLen, false, par);
1581 }
1582
1583 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1584 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1585 {
1586 if (tracing) {
1587 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1588 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1589 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1590 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1591 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1592 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1593 reader_EndTime = tag_StartTime - exact_fdt;
1594 reader_StartTime = reader_EndTime - reader_modlen;
1595 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1596 return FALSE;
1597 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1598 } else {
1599 return TRUE;
1600 }
1601 }
1602
1603 //-----------------------------------------------------------------------------
1604 // Wait a certain time for tag response
1605 // If a response is captured return TRUE
1606 // If it takes too long return FALSE
1607 //-----------------------------------------------------------------------------
1608 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1609 {
1610 uint32_t c;
1611
1612 // Set FPGA mode to "reader listen mode", no modulation (listen
1613 // only, since we are receiving, not transmitting).
1614 // Signal field is on with the appropriate LED
1615 LED_D_ON();
1616 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1617
1618 // Now get the answer from the card
1619 DemodInit(receivedResponse, receivedResponsePar);
1620
1621 // clear RXRDY:
1622 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1623
1624 c = 0;
1625 for(;;) {
1626 WDT_HIT();
1627
1628 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1629 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1630 if(ManchesterDecoding(b, offset, 0)) {
1631 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1632 return TRUE;
1633 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1634 return FALSE;
1635 }
1636 }
1637 }
1638 }
1639
1640
1641 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1642 {
1643 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1644
1645 // Send command to tag
1646 TransmitFor14443a(ToSend, ToSendMax, timing);
1647 if(trigger)
1648 LED_A_ON();
1649
1650 // Log reader command in trace buffer
1651 if (tracing) {
1652 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1653 }
1654 }
1655
1656
1657 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1658 {
1659 ReaderTransmitBitsPar(frame, len*8, par, timing);
1660 }
1661
1662
1663 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1664 {
1665 // Generate parity and redirect
1666 uint8_t par[MAX_PARITY_SIZE];
1667 GetParity(frame, len/8, par);
1668 ReaderTransmitBitsPar(frame, len, par, timing);
1669 }
1670
1671
1672 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1673 {
1674 // Generate parity and redirect
1675 uint8_t par[MAX_PARITY_SIZE];
1676 GetParity(frame, len, par);
1677 ReaderTransmitBitsPar(frame, len*8, par, timing);
1678 }
1679
1680 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1681 {
1682 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1683 if (tracing) {
1684 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1685 }
1686 return Demod.len;
1687 }
1688
1689 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1690 {
1691 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1692 if (tracing) {
1693 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1694 }
1695 return Demod.len;
1696 }
1697
1698 /* performs iso14443a anticollision procedure
1699 * fills the uid pointer unless NULL
1700 * fills resp_data unless NULL */
1701 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1702 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1703 uint8_t sel_all[] = { 0x93,0x20 };
1704 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1705 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1706 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1707 uint8_t resp_par[MAX_PARITY_SIZE];
1708 byte_t uid_resp[4];
1709 size_t uid_resp_len;
1710
1711 uint8_t sak = 0x04; // cascade uid
1712 int cascade_level = 0;
1713 int len;
1714
1715 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1716 ReaderTransmitBitsPar(wupa,7,0, NULL);
1717
1718 // Receive the ATQA
1719 if(!ReaderReceive(resp, resp_par)) return 0;
1720
1721 if(p_hi14a_card) {
1722 memcpy(p_hi14a_card->atqa, resp, 2);
1723 p_hi14a_card->uidlen = 0;
1724 memset(p_hi14a_card->uid,0,10);
1725 }
1726
1727 // clear uid
1728 if (uid_ptr) {
1729 memset(uid_ptr,0,10);
1730 }
1731
1732 // check for proprietary anticollision:
1733 if ((resp[0] & 0x1F) == 0) {
1734 return 3;
1735 }
1736
1737 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1738 // which case we need to make a cascade 2 request and select - this is a long UID
1739 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1740 for(; sak & 0x04; cascade_level++) {
1741 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1742 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1743
1744 // SELECT_ALL
1745 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1746 if (!ReaderReceive(resp, resp_par)) return 0;
1747
1748 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1749 memset(uid_resp, 0, 4);
1750 uint16_t uid_resp_bits = 0;
1751 uint16_t collision_answer_offset = 0;
1752 // anti-collision-loop:
1753 while (Demod.collisionPos) {
1754 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1755 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1756 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1757 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1758 }
1759 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1760 uid_resp_bits++;
1761 // construct anticollosion command:
1762 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1763 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1764 sel_uid[2+i] = uid_resp[i];
1765 }
1766 collision_answer_offset = uid_resp_bits%8;
1767 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1768 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1769 }
1770 // finally, add the last bits and BCC of the UID
1771 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1772 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1773 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1774 }
1775
1776 } else { // no collision, use the response to SELECT_ALL as current uid
1777 memcpy(uid_resp, resp, 4);
1778 }
1779 uid_resp_len = 4;
1780
1781 // calculate crypto UID. Always use last 4 Bytes.
1782 if(cuid_ptr) {
1783 *cuid_ptr = bytes_to_num(uid_resp, 4);
1784 }
1785
1786 // Construct SELECT UID command
1787 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1788 memcpy(sel_uid+2, uid_resp, 4); // the UID
1789 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1790 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1791 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1792
1793 // Receive the SAK
1794 if (!ReaderReceive(resp, resp_par)) return 0;
1795 sak = resp[0];
1796
1797 // Test if more parts of the uid are coming
1798 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1799 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1800 // http://www.nxp.com/documents/application_note/AN10927.pdf
1801 uid_resp[0] = uid_resp[1];
1802 uid_resp[1] = uid_resp[2];
1803 uid_resp[2] = uid_resp[3];
1804
1805 uid_resp_len = 3;
1806 }
1807
1808 if(uid_ptr) {
1809 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1810 }
1811
1812 if(p_hi14a_card) {
1813 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1814 p_hi14a_card->uidlen += uid_resp_len;
1815 }
1816 }
1817
1818 if(p_hi14a_card) {
1819 p_hi14a_card->sak = sak;
1820 p_hi14a_card->ats_len = 0;
1821 }
1822
1823 // non iso14443a compliant tag
1824 if( (sak & 0x20) == 0) return 2;
1825
1826 // Request for answer to select
1827 AppendCrc14443a(rats, 2);
1828 ReaderTransmit(rats, sizeof(rats), NULL);
1829
1830 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1831
1832
1833 if(p_hi14a_card) {
1834 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1835 p_hi14a_card->ats_len = len;
1836 }
1837
1838 // reset the PCB block number
1839 iso14_pcb_blocknum = 0;
1840
1841 // set default timeout based on ATS
1842 iso14a_set_ATS_timeout(resp);
1843
1844 return 1;
1845 }
1846
1847 void iso14443a_setup(uint8_t fpga_minor_mode) {
1848 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1849 // Set up the synchronous serial port
1850 FpgaSetupSsc();
1851 // connect Demodulated Signal to ADC:
1852 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1853
1854 // Signal field is on with the appropriate LED
1855 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1856 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1857 LED_D_ON();
1858 } else {
1859 LED_D_OFF();
1860 }
1861 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1862
1863 // Start the timer
1864 StartCountSspClk();
1865
1866 DemodReset();
1867 UartReset();
1868 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1869 iso14a_set_timeout(1050); // 10ms default
1870 }
1871
1872 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1873 uint8_t parity[MAX_PARITY_SIZE];
1874 uint8_t real_cmd[cmd_len+4];
1875 real_cmd[0] = 0x0a; //I-Block
1876 // put block number into the PCB
1877 real_cmd[0] |= iso14_pcb_blocknum;
1878 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1879 memcpy(real_cmd+2, cmd, cmd_len);
1880 AppendCrc14443a(real_cmd,cmd_len+2);
1881
1882 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1883 size_t len = ReaderReceive(data, parity);
1884 uint8_t *data_bytes = (uint8_t *) data;
1885 if (!len)
1886 return 0; //DATA LINK ERROR
1887 // if we received an I- or R(ACK)-Block with a block number equal to the
1888 // current block number, toggle the current block number
1889 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1890 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1891 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1892 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1893 {
1894 iso14_pcb_blocknum ^= 1;
1895 }
1896
1897 return len;
1898 }
1899
1900 //-----------------------------------------------------------------------------
1901 // Read an ISO 14443a tag. Send out commands and store answers.
1902 //
1903 //-----------------------------------------------------------------------------
1904 void ReaderIso14443a(UsbCommand *c)
1905 {
1906 iso14a_command_t param = c->arg[0];
1907 uint8_t *cmd = c->d.asBytes;
1908 size_t len = c->arg[1] & 0xffff;
1909 size_t lenbits = c->arg[1] >> 16;
1910 uint32_t timeout = c->arg[2];
1911 uint32_t arg0 = 0;
1912 byte_t buf[USB_CMD_DATA_SIZE];
1913 uint8_t par[MAX_PARITY_SIZE];
1914
1915 if(param & ISO14A_CONNECT) {
1916 clear_trace();
1917 }
1918
1919 set_tracing(TRUE);
1920
1921 if(param & ISO14A_REQUEST_TRIGGER) {
1922 iso14a_set_trigger(TRUE);
1923 }
1924
1925 if(param & ISO14A_CONNECT) {
1926 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1927 if(!(param & ISO14A_NO_SELECT)) {
1928 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1929 arg0 = iso14443a_select_card(NULL,card,NULL);
1930 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1931 }
1932 }
1933
1934 if(param & ISO14A_SET_TIMEOUT) {
1935 iso14a_set_timeout(timeout);
1936 }
1937
1938 if(param & ISO14A_APDU) {
1939 arg0 = iso14_apdu(cmd, len, buf);
1940 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1941 }
1942
1943 if(param & ISO14A_RAW) {
1944 if(param & ISO14A_APPEND_CRC) {
1945 if(param & ISO14A_TOPAZMODE) {
1946 AppendCrc14443b(cmd,len);
1947 } else {
1948 AppendCrc14443a(cmd,len);
1949 }
1950 len += 2;
1951 if (lenbits) lenbits += 16;
1952 }
1953 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
1954 if(param & ISO14A_TOPAZMODE) {
1955 int bits_to_send = lenbits;
1956 uint16_t i = 0;
1957 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
1958 bits_to_send -= 7;
1959 while (bits_to_send > 0) {
1960 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
1961 bits_to_send -= 8;
1962 }
1963 } else {
1964 GetParity(cmd, lenbits/8, par);
1965 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
1966 }
1967 } else { // want to send complete bytes only
1968 if(param & ISO14A_TOPAZMODE) {
1969 uint16_t i = 0;
1970 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
1971 while (i < len) {
1972 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
1973 }
1974 } else {
1975 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
1976 }
1977 }
1978 arg0 = ReaderReceive(buf, par);
1979 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1980 }
1981
1982 if(param & ISO14A_REQUEST_TRIGGER) {
1983 iso14a_set_trigger(FALSE);
1984 }
1985
1986 if(param & ISO14A_NO_DISCONNECT) {
1987 return;
1988 }
1989
1990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1991 LEDsoff();
1992 }
1993
1994
1995 // Determine the distance between two nonces.
1996 // Assume that the difference is small, but we don't know which is first.
1997 // Therefore try in alternating directions.
1998 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1999
2000 uint16_t i;
2001 uint32_t nttmp1, nttmp2;
2002
2003 if (nt1 == nt2) return 0;
2004
2005 nttmp1 = nt1;
2006 nttmp2 = nt2;
2007
2008 for (i = 1; i < 32768; i++) {
2009 nttmp1 = prng_successor(nttmp1, 1);
2010 if (nttmp1 == nt2) return i;
2011 nttmp2 = prng_successor(nttmp2, 1);
2012 if (nttmp2 == nt1) return -i;
2013 }
2014
2015 return(-99999); // either nt1 or nt2 are invalid nonces
2016 }
2017
2018
2019 //-----------------------------------------------------------------------------
2020 // Recover several bits of the cypher stream. This implements (first stages of)
2021 // the algorithm described in "The Dark Side of Security by Obscurity and
2022 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2023 // (article by Nicolas T. Courtois, 2009)
2024 //-----------------------------------------------------------------------------
2025 void ReaderMifare(bool first_try)
2026 {
2027 // Mifare AUTH
2028 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2029 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2030 static uint8_t mf_nr_ar3;
2031
2032 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2033 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2034
2035 if (first_try) {
2036 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2037 }
2038
2039 // free eventually allocated BigBuf memory. We want all for tracing.
2040 BigBuf_free();
2041
2042 clear_trace();
2043 set_tracing(TRUE);
2044
2045 byte_t nt_diff = 0;
2046 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2047 static byte_t par_low = 0;
2048 bool led_on = TRUE;
2049 uint8_t uid[10] ={0};
2050 uint32_t cuid;
2051
2052 uint32_t nt = 0;
2053 uint32_t previous_nt = 0;
2054 static uint32_t nt_attacked = 0;
2055 byte_t par_list[8] = {0x00};
2056 byte_t ks_list[8] = {0x00};
2057
2058 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2059 static uint32_t sync_time;
2060 static int32_t sync_cycles;
2061 int catch_up_cycles = 0;
2062 int last_catch_up = 0;
2063 uint16_t elapsed_prng_sequences;
2064 uint16_t consecutive_resyncs = 0;
2065 int isOK = 0;
2066
2067 if (first_try) {
2068 mf_nr_ar3 = 0;
2069 sync_time = GetCountSspClk() & 0xfffffff8;
2070 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2071 nt_attacked = 0;
2072 par[0] = 0;
2073 }
2074 else {
2075 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2076 mf_nr_ar3++;
2077 mf_nr_ar[3] = mf_nr_ar3;
2078 par[0] = par_low;
2079 }
2080
2081 LED_A_ON();
2082 LED_B_OFF();
2083 LED_C_OFF();
2084
2085
2086 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2087 #define MAX_SYNC_TRIES 32
2088 #define NUM_DEBUG_INFOS 8 // per strategy
2089 #define MAX_STRATEGY 3
2090 uint16_t unexpected_random = 0;
2091 uint16_t sync_tries = 0;
2092 int16_t debug_info_nr = -1;
2093 uint16_t strategy = 0;
2094 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2095 uint32_t select_time;
2096 uint32_t halt_time;
2097
2098 for(uint16_t i = 0; TRUE; i++) {
2099
2100 LED_C_ON();
2101 WDT_HIT();
2102
2103 // Test if the action was cancelled
2104 if(BUTTON_PRESS()) {
2105 isOK = -1;
2106 break;
2107 }
2108
2109 if (strategy == 2) {
2110 // test with additional hlt command
2111 halt_time = 0;
2112 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2113 if (len && MF_DBGLEVEL >= 3) {
2114 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2115 }
2116 }
2117
2118 if (strategy == 3) {
2119 // test with FPGA power off/on
2120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2121 SpinDelay(200);
2122 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2123 SpinDelay(100);
2124 }
2125
2126 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2127 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2128 continue;
2129 }
2130 select_time = GetCountSspClk();
2131
2132 elapsed_prng_sequences = 1;
2133 if (debug_info_nr == -1) {
2134 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2135 catch_up_cycles = 0;
2136
2137 // if we missed the sync time already, advance to the next nonce repeat
2138 while(GetCountSspClk() > sync_time) {
2139 elapsed_prng_sequences++;
2140 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2141 }
2142
2143 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2144 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2145 } else {
2146 // collect some information on tag nonces for debugging:
2147 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2148 if (strategy == 0) {
2149 // nonce distances at fixed time after card select:
2150 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2151 } else if (strategy == 1) {
2152 // nonce distances at fixed time between authentications:
2153 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2154 } else if (strategy == 2) {
2155 // nonce distances at fixed time after halt:
2156 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2157 } else {
2158 // nonce_distances at fixed time after power on
2159 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2160 }
2161 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2162 }
2163
2164 // Receive the (4 Byte) "random" nonce
2165 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2166 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2167 continue;
2168 }
2169
2170 previous_nt = nt;
2171 nt = bytes_to_num(receivedAnswer, 4);
2172
2173 // Transmit reader nonce with fake par
2174 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2175
2176 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2177 int nt_distance = dist_nt(previous_nt, nt);
2178 if (nt_distance == 0) {
2179 nt_attacked = nt;
2180 } else {
2181 if (nt_distance == -99999) { // invalid nonce received
2182 unexpected_random++;
2183 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2184 isOK = -3; // Card has an unpredictable PRNG. Give up
2185 break;
2186 } else {
2187 continue; // continue trying...
2188 }
2189 }
2190 if (++sync_tries > MAX_SYNC_TRIES) {
2191 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
2192 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2193 break;
2194 } else { // continue for a while, just to collect some debug info
2195 debug_info[strategy][debug_info_nr] = nt_distance;
2196 debug_info_nr++;
2197 if (debug_info_nr == NUM_DEBUG_INFOS) {
2198 strategy++;
2199 debug_info_nr = 0;
2200 }
2201 continue;
2202 }
2203 }
2204 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
2205 if (sync_cycles <= 0) {
2206 sync_cycles += PRNG_SEQUENCE_LENGTH;
2207 }
2208 if (MF_DBGLEVEL >= 3) {
2209 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2210 }
2211 continue;
2212 }
2213 }
2214
2215 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2216 catch_up_cycles = -dist_nt(nt_attacked, nt);
2217 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2218 catch_up_cycles = 0;
2219 continue;
2220 }
2221 catch_up_cycles /= elapsed_prng_sequences;
2222 if (catch_up_cycles == last_catch_up) {
2223 consecutive_resyncs++;
2224 }
2225 else {
2226 last_catch_up = catch_up_cycles;
2227 consecutive_resyncs = 0;
2228 }
2229 if (consecutive_resyncs < 3) {
2230 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2231 }
2232 else {
2233 sync_cycles = sync_cycles + catch_up_cycles;
2234 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2235 last_catch_up = 0;
2236 catch_up_cycles = 0;
2237 consecutive_resyncs = 0;
2238 }
2239 continue;
2240 }
2241
2242 consecutive_resyncs = 0;
2243
2244 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2245 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2246 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2247
2248 if (nt_diff == 0) {
2249 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2250 }
2251
2252 led_on = !led_on;
2253 if(led_on) LED_B_ON(); else LED_B_OFF();
2254
2255 par_list[nt_diff] = SwapBits(par[0], 8);
2256 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2257
2258 // Test if the information is complete
2259 if (nt_diff == 0x07) {
2260 isOK = 1;
2261 break;
2262 }
2263
2264 nt_diff = (nt_diff + 1) & 0x07;
2265 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2266 par[0] = par_low;
2267 } else {
2268 if (nt_diff == 0 && first_try)
2269 {
2270 par[0]++;
2271 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2272 isOK = -2;
2273 break;
2274 }
2275 } else {
2276 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2277 }
2278 }
2279 }
2280
2281
2282 mf_nr_ar[3] &= 0x1F;
2283
2284 if (isOK == -4) {
2285 if (MF_DBGLEVEL >= 3) {
2286 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2287 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2288 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2289 }
2290 }
2291 }
2292 }
2293
2294 byte_t buf[28];
2295 memcpy(buf + 0, uid, 4);
2296 num_to_bytes(nt, 4, buf + 4);
2297 memcpy(buf + 8, par_list, 8);
2298 memcpy(buf + 16, ks_list, 8);
2299 memcpy(buf + 24, mf_nr_ar, 4);
2300
2301 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
2302
2303 // Thats it...
2304 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2305 LEDsoff();
2306
2307 set_tracing(FALSE);
2308 }
2309
2310 /**
2311 *MIFARE 1K simulate.
2312 *
2313 *@param flags :
2314 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2315 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2316 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2317 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2318 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2319 */
2320 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2321 {
2322 int cardSTATE = MFEMUL_NOFIELD;
2323 int _7BUID = 0;
2324 int vHf = 0; // in mV
2325 int res;
2326 uint32_t selTimer = 0;
2327 uint32_t authTimer = 0;
2328 uint16_t len = 0;
2329 uint8_t cardWRBL = 0;
2330 uint8_t cardAUTHSC = 0;
2331 uint8_t cardAUTHKEY = 0xff; // no authentication
2332 uint32_t cardRr = 0;
2333 uint32_t cuid = 0;
2334 //uint32_t rn_enc = 0;
2335 uint32_t ans = 0;
2336 uint32_t cardINTREG = 0;
2337 uint8_t cardINTBLOCK = 0;
2338 struct Crypto1State mpcs = {0, 0};
2339 struct Crypto1State *pcs;
2340 pcs = &mpcs;
2341 uint32_t numReads = 0;//Counts numer of times reader read a block
2342 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2343 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2344 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2345 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2346
2347 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2348 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2349 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2350 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2351 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2352
2353 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2354 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2355
2356 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2357 // This can be used in a reader-only attack.
2358 // (it can also be retrieved via 'hf 14a list', but hey...
2359 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2360 uint8_t ar_nr_collected = 0;
2361
2362 // Authenticate response - nonce
2363 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2364
2365 //-- Determine the UID
2366 // Can be set from emulator memory, incoming data
2367 // and can be 7 or 4 bytes long
2368 if (flags & FLAG_4B_UID_IN_DATA)
2369 {
2370 // 4B uid comes from data-portion of packet
2371 memcpy(rUIDBCC1,datain,4);
2372 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2373
2374 } else if (flags & FLAG_7B_UID_IN_DATA) {
2375 // 7B uid comes from data-portion of packet
2376 memcpy(&rUIDBCC1[1],datain,3);
2377 memcpy(rUIDBCC2, datain+3, 4);
2378 _7BUID = true;
2379 } else {
2380 // get UID from emul memory
2381 emlGetMemBt(receivedCmd, 7, 1);
2382 _7BUID = !(receivedCmd[0] == 0x00);
2383 if (!_7BUID) { // ---------- 4BUID
2384 emlGetMemBt(rUIDBCC1, 0, 4);
2385 } else { // ---------- 7BUID
2386 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2387 emlGetMemBt(rUIDBCC2, 3, 4);
2388 }
2389 }
2390
2391 /*
2392 * Regardless of what method was used to set the UID, set fifth byte and modify
2393 * the ATQA for 4 or 7-byte UID
2394 */
2395 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2396 if (_7BUID) {
2397 rATQA[0] = 0x44;
2398 rUIDBCC1[0] = 0x88;
2399 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2400 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2401 }
2402
2403 if (MF_DBGLEVEL >= 1) {
2404 if (!_7BUID) {
2405 Dbprintf("4B UID: %02x%02x%02x%02x",
2406 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2407 } else {
2408 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2409 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2410 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2411 }
2412 }
2413
2414 // We need to listen to the high-frequency, peak-detected path.
2415 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2416
2417 // free eventually allocated BigBuf memory but keep Emulator Memory
2418 BigBuf_free_keep_EM();
2419
2420 // clear trace
2421 clear_trace();
2422 set_tracing(TRUE);
2423
2424
2425 bool finished = FALSE;
2426 while (!BUTTON_PRESS() && !finished) {
2427 WDT_HIT();
2428
2429 // find reader field
2430 if (cardSTATE == MFEMUL_NOFIELD) {
2431 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2432 if (vHf > MF_MINFIELDV) {
2433 cardSTATE_TO_IDLE();
2434 LED_A_ON();
2435 }
2436 }
2437 if(cardSTATE == MFEMUL_NOFIELD) continue;
2438
2439 //Now, get data
2440
2441 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2442 if (res == 2) { //Field is off!
2443 cardSTATE = MFEMUL_NOFIELD;
2444 LEDsoff();
2445 continue;
2446 } else if (res == 1) {
2447 break; //return value 1 means button press
2448 }
2449
2450 // REQ or WUP request in ANY state and WUP in HALTED state
2451 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2452 selTimer = GetTickCount();
2453 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2454 cardSTATE = MFEMUL_SELECT1;
2455
2456 // init crypto block
2457 LED_B_OFF();
2458 LED_C_OFF();
2459 crypto1_destroy(pcs);
2460 cardAUTHKEY = 0xff;
2461 continue;
2462 }
2463
2464 switch (cardSTATE) {
2465 case MFEMUL_NOFIELD:
2466 case MFEMUL_HALTED:
2467 case MFEMUL_IDLE:{
2468 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2469 break;
2470 }
2471 case MFEMUL_SELECT1:{
2472 // select all
2473 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2474 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2475 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2476 break;
2477 }
2478
2479 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2480 {
2481 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2482 }
2483 // select card
2484 if (len == 9 &&
2485 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2486 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2487 cuid = bytes_to_num(rUIDBCC1, 4);
2488 if (!_7BUID) {
2489 cardSTATE = MFEMUL_WORK;
2490 LED_B_ON();
2491 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2492 break;
2493 } else {
2494 cardSTATE = MFEMUL_SELECT2;
2495 }
2496 }
2497 break;
2498 }
2499 case MFEMUL_AUTH1:{
2500 if( len != 8)
2501 {
2502 cardSTATE_TO_IDLE();
2503 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2504 break;
2505 }
2506
2507 uint32_t ar = bytes_to_num(receivedCmd, 4);
2508 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2509
2510 //Collect AR/NR
2511 if(ar_nr_collected < 2){
2512 if(ar_nr_responses[2] != ar)
2513 {// Avoid duplicates... probably not necessary, ar should vary.
2514 ar_nr_responses[ar_nr_collected*4] = cuid;
2515 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2516 ar_nr_responses[ar_nr_collected*4+2] = ar;
2517 ar_nr_responses[ar_nr_collected*4+3] = nr;
2518 ar_nr_collected++;
2519 }
2520 }
2521
2522 // --- crypto
2523 crypto1_word(pcs, ar , 1);
2524 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2525
2526 // test if auth OK
2527 if (cardRr != prng_successor(nonce, 64)){
2528 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2529 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2530 cardRr, prng_successor(nonce, 64));
2531 // Shouldn't we respond anything here?
2532 // Right now, we don't nack or anything, which causes the
2533 // reader to do a WUPA after a while. /Martin
2534 // -- which is the correct response. /piwi
2535 cardSTATE_TO_IDLE();
2536 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2537 break;
2538 }
2539
2540 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2541
2542 num_to_bytes(ans, 4, rAUTH_AT);
2543 // --- crypto
2544 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2545 LED_C_ON();
2546 cardSTATE = MFEMUL_WORK;
2547 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2548 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2549 GetTickCount() - authTimer);
2550 break;
2551 }
2552 case MFEMUL_SELECT2:{
2553 if (!len) {
2554 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2555 break;
2556 }
2557 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2558 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2559 break;
2560 }
2561
2562 // select 2 card
2563 if (len == 9 &&
2564 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2565 EmSendCmd(rSAK, sizeof(rSAK));
2566 cuid = bytes_to_num(rUIDBCC2, 4);
2567 cardSTATE = MFEMUL_WORK;
2568 LED_B_ON();
2569 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2570 break;
2571 }
2572
2573 // i guess there is a command). go into the work state.
2574 if (len != 4) {
2575 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2576 break;
2577 }
2578 cardSTATE = MFEMUL_WORK;
2579 //goto lbWORK;
2580 //intentional fall-through to the next case-stmt
2581 }
2582
2583 case MFEMUL_WORK:{
2584 if (len == 0) {
2585 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2586 break;
2587 }
2588
2589 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2590
2591 if(encrypted_data) {
2592 // decrypt seqence
2593 mf_crypto1_decrypt(pcs, receivedCmd, len);
2594 }
2595
2596 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2597 authTimer = GetTickCount();
2598 cardAUTHSC = receivedCmd[1] / 4; // received block num
2599 cardAUTHKEY = receivedCmd[0] - 0x60;
2600 crypto1_destroy(pcs);//Added by martin
2601 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2602
2603 if (!encrypted_data) { // first authentication
2604 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2605
2606 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2607 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2608 } else { // nested authentication
2609 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2610 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2611 num_to_bytes(ans, 4, rAUTH_AT);
2612 }
2613
2614 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2615 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2616 cardSTATE = MFEMUL_AUTH1;
2617 break;
2618 }
2619
2620 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2621 // BUT... ACK --> NACK
2622 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2623 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2624 break;
2625 }
2626
2627 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2628 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2629 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2630 break;
2631 }
2632
2633 if(len != 4) {
2634 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2635 break;
2636 }
2637
2638 if(receivedCmd[0] == 0x30 // read block
2639 || receivedCmd[0] == 0xA0 // write block
2640 || receivedCmd[0] == 0xC0 // inc
2641 || receivedCmd[0] == 0xC1 // dec
2642 || receivedCmd[0] == 0xC2 // restore
2643 || receivedCmd[0] == 0xB0) { // transfer
2644 if (receivedCmd[1] >= 16 * 4) {
2645 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2646 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2647 break;
2648 }
2649
2650 if (receivedCmd[1] / 4 != cardAUTHSC) {
2651 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2652 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2653 break;
2654 }
2655 }
2656 // read block
2657 if (receivedCmd[0] == 0x30) {
2658 if (MF_DBGLEVEL >= 4) {
2659 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2660 }
2661 emlGetMem(response, receivedCmd[1], 1);
2662 AppendCrc14443a(response, 16);
2663 mf_crypto1_encrypt(pcs, response, 18, response_par);
2664 EmSendCmdPar(response, 18, response_par);
2665 numReads++;
2666 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2667 Dbprintf("%d reads done, exiting", numReads);
2668 finished = true;
2669 }
2670 break;
2671 }
2672 // write block
2673 if (receivedCmd[0] == 0xA0) {
2674 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2675 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2676 cardSTATE = MFEMUL_WRITEBL2;
2677 cardWRBL = receivedCmd[1];
2678 break;
2679 }
2680 // increment, decrement, restore
2681 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2682 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2683 if (emlCheckValBl(receivedCmd[1])) {
2684 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2685 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2686 break;
2687 }
2688 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2689 if (receivedCmd[0] == 0xC1)
2690 cardSTATE = MFEMUL_INTREG_INC;
2691 if (receivedCmd[0] == 0xC0)
2692 cardSTATE = MFEMUL_INTREG_DEC;
2693 if (receivedCmd[0] == 0xC2)
2694 cardSTATE = MFEMUL_INTREG_REST;
2695 cardWRBL = receivedCmd[1];
2696 break;
2697 }
2698 // transfer
2699 if (receivedCmd[0] == 0xB0) {
2700 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2701 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2702 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2703 else
2704 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2705 break;
2706 }
2707 // halt
2708 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2709 LED_B_OFF();
2710 LED_C_OFF();
2711 cardSTATE = MFEMUL_HALTED;
2712 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2713 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2714 break;
2715 }
2716 // RATS
2717 if (receivedCmd[0] == 0xe0) {//RATS
2718 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2719 break;
2720 }
2721 // command not allowed
2722 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2723 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2724 break;
2725 }
2726 case MFEMUL_WRITEBL2:{
2727 if (len == 18){
2728 mf_crypto1_decrypt(pcs, receivedCmd, len);
2729 emlSetMem(receivedCmd, cardWRBL, 1);
2730 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2731 cardSTATE = MFEMUL_WORK;
2732 } else {
2733 cardSTATE_TO_IDLE();
2734 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2735 }
2736 break;
2737 }
2738
2739 case MFEMUL_INTREG_INC:{
2740 mf_crypto1_decrypt(pcs, receivedCmd, len);
2741 memcpy(&ans, receivedCmd, 4);
2742 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2743 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2744 cardSTATE_TO_IDLE();
2745 break;
2746 }
2747 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2748 cardINTREG = cardINTREG + ans;
2749 cardSTATE = MFEMUL_WORK;
2750 break;
2751 }
2752 case MFEMUL_INTREG_DEC:{
2753 mf_crypto1_decrypt(pcs, receivedCmd, len);
2754 memcpy(&ans, receivedCmd, 4);
2755 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2756 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2757 cardSTATE_TO_IDLE();
2758 break;
2759 }
2760 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2761 cardINTREG = cardINTREG - ans;
2762 cardSTATE = MFEMUL_WORK;
2763 break;
2764 }
2765 case MFEMUL_INTREG_REST:{
2766 mf_crypto1_decrypt(pcs, receivedCmd, len);
2767 memcpy(&ans, receivedCmd, 4);
2768 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2769 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2770 cardSTATE_TO_IDLE();
2771 break;
2772 }
2773 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2774 cardSTATE = MFEMUL_WORK;
2775 break;
2776 }
2777 }
2778 }
2779
2780 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2781 LEDsoff();
2782
2783 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2784 {
2785 //May just aswell send the collected ar_nr in the response aswell
2786 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2787 }
2788
2789 if(flags & FLAG_NR_AR_ATTACK)
2790 {
2791 if(ar_nr_collected > 1) {
2792 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2793 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2794 ar_nr_responses[0], // UID
2795 ar_nr_responses[1], //NT
2796 ar_nr_responses[2], //AR1
2797 ar_nr_responses[3], //NR1
2798 ar_nr_responses[6], //AR2
2799 ar_nr_responses[7] //NR2
2800 );
2801 } else {
2802 Dbprintf("Failed to obtain two AR/NR pairs!");
2803 if(ar_nr_collected >0) {
2804 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2805 ar_nr_responses[0], // UID
2806 ar_nr_responses[1], //NT
2807 ar_nr_responses[2], //AR1
2808 ar_nr_responses[3] //NR1
2809 );
2810 }
2811 }
2812 }
2813 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2814
2815 }
2816
2817
2818
2819 //-----------------------------------------------------------------------------
2820 // MIFARE sniffer.
2821 //
2822 //-----------------------------------------------------------------------------
2823 void RAMFUNC SniffMifare(uint8_t param) {
2824 // param:
2825 // bit 0 - trigger from first card answer
2826 // bit 1 - trigger from first reader 7-bit request
2827
2828 // C(red) A(yellow) B(green)
2829 LEDsoff();
2830 // init trace buffer
2831 clear_trace();
2832 set_tracing(TRUE);
2833
2834 // The command (reader -> tag) that we're receiving.
2835 // The length of a received command will in most cases be no more than 18 bytes.
2836 // So 32 should be enough!
2837 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2838 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2839 // The response (tag -> reader) that we're receiving.
2840 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2841 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2842
2843 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2844
2845 // free eventually allocated BigBuf memory
2846 BigBuf_free();
2847 // allocate the DMA buffer, used to stream samples from the FPGA
2848 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2849 uint8_t *data = dmaBuf;
2850 uint8_t previous_data = 0;
2851 int maxDataLen = 0;
2852 int dataLen = 0;
2853 bool ReaderIsActive = FALSE;
2854 bool TagIsActive = FALSE;
2855
2856 // Set up the demodulator for tag -> reader responses.
2857 DemodInit(receivedResponse, receivedResponsePar);
2858
2859 // Set up the demodulator for the reader -> tag commands
2860 UartInit(receivedCmd, receivedCmdPar);
2861
2862 // Setup for the DMA.
2863 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2864
2865 LED_D_OFF();
2866
2867 // init sniffer
2868 MfSniffInit();
2869
2870 // And now we loop, receiving samples.
2871 for(uint32_t sniffCounter = 0; TRUE; ) {
2872
2873 if(BUTTON_PRESS()) {
2874 DbpString("cancelled by button");
2875 break;
2876 }
2877
2878 LED_A_ON();
2879 WDT_HIT();
2880
2881 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2882 // check if a transaction is completed (timeout after 2000ms).
2883 // if yes, stop the DMA transfer and send what we have so far to the client
2884 if (MfSniffSend(2000)) {
2885 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2886 sniffCounter = 0;
2887 data = dmaBuf;
2888 maxDataLen = 0;
2889 ReaderIsActive = FALSE;
2890 TagIsActive = FALSE;
2891 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2892 }
2893 }
2894
2895 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2896 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2897 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2898 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2899 } else {
2900 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2901 }
2902 // test for length of buffer
2903 if(dataLen > maxDataLen) { // we are more behind than ever...
2904 maxDataLen = dataLen;
2905 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2906 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2907 break;
2908 }
2909 }
2910 if(dataLen < 1) continue;
2911
2912 // primary buffer was stopped ( <-- we lost data!
2913 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2914 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2915 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2916 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2917 }
2918 // secondary buffer sets as primary, secondary buffer was stopped
2919 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2920 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2921 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2922 }
2923
2924 LED_A_OFF();
2925
2926 if (sniffCounter & 0x01) {
2927
2928 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2929 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2930 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2931 LED_C_INV();
2932 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2933
2934 /* And ready to receive another command. */
2935 UartInit(receivedCmd, receivedCmdPar);
2936
2937 /* And also reset the demod code */
2938 DemodReset();
2939 }
2940 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2941 }
2942
2943 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2944 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2945 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2946 LED_C_INV();
2947
2948 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2949
2950 // And ready to receive another response.
2951 DemodReset();
2952 // And reset the Miller decoder including its (now outdated) input buffer
2953 UartInit(receivedCmd, receivedCmdPar);
2954 }
2955 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2956 }
2957 }
2958
2959 previous_data = *data;
2960 sniffCounter++;
2961 data++;
2962 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2963 data = dmaBuf;
2964 }
2965
2966 } // main cycle
2967
2968 DbpString("COMMAND FINISHED");
2969
2970 FpgaDisableSscDma();
2971 MfSniffEnd();
2972
2973 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2974 LEDsoff();
2975 }
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