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Added the changes to armsrc for milfare ultralight C and Desfire commands
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18 void LFSetupFPGAForADC(int divisor, bool lf_field)
19 {
20 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
21 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
22 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
23 else if (divisor == 0)
24 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
25 else
26 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
27
28 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
29
30 // Connect the A/D to the peak-detected low-frequency path.
31 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
32 // Give it a bit of time for the resonant antenna to settle.
33 SpinDelay(50);
34 // Now set up the SSC to get the ADC samples that are now streaming at us.
35 FpgaSetupSsc();
36 }
37
38 void AcquireRawAdcSamples125k(int divisor)
39 {
40 LFSetupFPGAForADC(divisor, true);
41 DoAcquisition125k(-1);
42 }
43
44 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
45 {
46 LFSetupFPGAForADC(divisor, false);
47 DoAcquisition125k(trigger_threshold);
48 }
49
50 // split into two routines so we can avoid timing issues after sending commands //
51 void DoAcquisition125k(int trigger_threshold)
52 {
53 uint8_t *dest = (uint8_t *)BigBuf;
54 int n = sizeof(BigBuf);
55 int i;
56
57 memset(dest, 0, n);
58 i = 0;
59 for(;;) {
60 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
61 AT91C_BASE_SSC->SSC_THR = 0x43;
62 LED_D_ON();
63 }
64 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
65 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
66 LED_D_OFF();
67 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
68 continue;
69 else
70 trigger_threshold = -1;
71 if (++i >= n) break;
72 }
73 }
74 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
75 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
76 }
77
78 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
79 {
80 int at134khz;
81
82 /* Make sure the tag is reset */
83 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
84 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
85 SpinDelay(2500);
86
87 // see if 'h' was specified
88 if (command[strlen((char *) command) - 1] == 'h')
89 at134khz = TRUE;
90 else
91 at134khz = FALSE;
92
93 if (at134khz)
94 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
95 else
96 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
97
98 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
99
100 // Give it a bit of time for the resonant antenna to settle.
101 SpinDelay(50);
102 // And a little more time for the tag to fully power up
103 SpinDelay(2000);
104
105 // Now set up the SSC to get the ADC samples that are now streaming at us.
106 FpgaSetupSsc();
107
108 // now modulate the reader field
109 while(*command != '\0' && *command != ' ') {
110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
111 LED_D_OFF();
112 SpinDelayUs(delay_off);
113 if (at134khz)
114 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
115 else
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
117
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
119 LED_D_ON();
120 if(*(command++) == '0')
121 SpinDelayUs(period_0);
122 else
123 SpinDelayUs(period_1);
124 }
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
126 LED_D_OFF();
127 SpinDelayUs(delay_off);
128 if (at134khz)
129 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
130 else
131 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
132
133 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
134
135 // now do the read
136 DoAcquisition125k(-1);
137 }
138
139 /* blank r/w tag data stream
140 ...0000000000000000 01111111
141 1010101010101010101010101010101010101010101010101010101010101010
142 0011010010100001
143 01111111
144 101010101010101[0]000...
145
146 [5555fe852c5555555555555555fe0000]
147 */
148 void ReadTItag(void)
149 {
150 // some hardcoded initial params
151 // when we read a TI tag we sample the zerocross line at 2Mhz
152 // TI tags modulate a 1 as 16 cycles of 123.2Khz
153 // TI tags modulate a 0 as 16 cycles of 134.2Khz
154 #define FSAMPLE 2000000
155 #define FREQLO 123200
156 #define FREQHI 134200
157
158 signed char *dest = (signed char *)BigBuf;
159 int n = sizeof(BigBuf);
160 // int *dest = GraphBuffer;
161 // int n = GraphTraceLen;
162
163 // 128 bit shift register [shift3:shift2:shift1:shift0]
164 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
165
166 int i, cycles=0, samples=0;
167 // how many sample points fit in 16 cycles of each frequency
168 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
169 // when to tell if we're close enough to one freq or another
170 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
171
172 // TI tags charge at 134.2Khz
173 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
174 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
175
176 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
177 // connects to SSP_DIN and the SSP_DOUT logic level controls
178 // whether we're modulating the antenna (high)
179 // or listening to the antenna (low)
180 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
181
182 // get TI tag data into the buffer
183 AcquireTiType();
184
185 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
186
187 for (i=0; i<n-1; i++) {
188 // count cycles by looking for lo to hi zero crossings
189 if ( (dest[i]<0) && (dest[i+1]>0) ) {
190 cycles++;
191 // after 16 cycles, measure the frequency
192 if (cycles>15) {
193 cycles=0;
194 samples=i-samples; // number of samples in these 16 cycles
195
196 // TI bits are coming to us lsb first so shift them
197 // right through our 128 bit right shift register
198 shift0 = (shift0>>1) | (shift1 << 31);
199 shift1 = (shift1>>1) | (shift2 << 31);
200 shift2 = (shift2>>1) | (shift3 << 31);
201 shift3 >>= 1;
202
203 // check if the cycles fall close to the number
204 // expected for either the low or high frequency
205 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
206 // low frequency represents a 1
207 shift3 |= (1<<31);
208 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
209 // high frequency represents a 0
210 } else {
211 // probably detected a gay waveform or noise
212 // use this as gaydar or discard shift register and start again
213 shift3 = shift2 = shift1 = shift0 = 0;
214 }
215 samples = i;
216
217 // for each bit we receive, test if we've detected a valid tag
218
219 // if we see 17 zeroes followed by 6 ones, we might have a tag
220 // remember the bits are backwards
221 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
222 // if start and end bytes match, we have a tag so break out of the loop
223 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
224 cycles = 0xF0B; //use this as a flag (ugly but whatever)
225 break;
226 }
227 }
228 }
229 }
230 }
231
232 // if flag is set we have a tag
233 if (cycles!=0xF0B) {
234 DbpString("Info: No valid tag detected.");
235 } else {
236 // put 64 bit data into shift1 and shift0
237 shift0 = (shift0>>24) | (shift1 << 8);
238 shift1 = (shift1>>24) | (shift2 << 8);
239
240 // align 16 bit crc into lower half of shift2
241 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
242
243 // if r/w tag, check ident match
244 if ( shift3&(1<<15) ) {
245 DbpString("Info: TI tag is rewriteable");
246 // only 15 bits compare, last bit of ident is not valid
247 if ( ((shift3>>16)^shift0)&0x7fff ) {
248 DbpString("Error: Ident mismatch!");
249 } else {
250 DbpString("Info: TI tag ident is valid");
251 }
252 } else {
253 DbpString("Info: TI tag is readonly");
254 }
255
256 // WARNING the order of the bytes in which we calc crc below needs checking
257 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
258 // bytes in reverse or something
259 // calculate CRC
260 uint32_t crc=0;
261
262 crc = update_crc16(crc, (shift0)&0xff);
263 crc = update_crc16(crc, (shift0>>8)&0xff);
264 crc = update_crc16(crc, (shift0>>16)&0xff);
265 crc = update_crc16(crc, (shift0>>24)&0xff);
266 crc = update_crc16(crc, (shift1)&0xff);
267 crc = update_crc16(crc, (shift1>>8)&0xff);
268 crc = update_crc16(crc, (shift1>>16)&0xff);
269 crc = update_crc16(crc, (shift1>>24)&0xff);
270
271 Dbprintf("Info: Tag data: %x%08x, crc=%x",
272 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
273 if (crc != (shift2&0xffff)) {
274 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
275 } else {
276 DbpString("Info: CRC is good");
277 }
278 }
279 }
280
281 void WriteTIbyte(uint8_t b)
282 {
283 int i = 0;
284
285 // modulate 8 bits out to the antenna
286 for (i=0; i<8; i++)
287 {
288 if (b&(1<<i)) {
289 // stop modulating antenna
290 LOW(GPIO_SSC_DOUT);
291 SpinDelayUs(1000);
292 // modulate antenna
293 HIGH(GPIO_SSC_DOUT);
294 SpinDelayUs(1000);
295 } else {
296 // stop modulating antenna
297 LOW(GPIO_SSC_DOUT);
298 SpinDelayUs(300);
299 // modulate antenna
300 HIGH(GPIO_SSC_DOUT);
301 SpinDelayUs(1700);
302 }
303 }
304 }
305
306 void AcquireTiType(void)
307 {
308 int i, j, n;
309 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
310 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
311 #define TIBUFLEN 1250
312
313 // clear buffer
314 memset(BigBuf,0,sizeof(BigBuf));
315
316 // Set up the synchronous serial port
317 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
318 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
319
320 // steal this pin from the SSP and use it to control the modulation
321 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
322 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
323
324 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
325 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
326
327 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
328 // 48/2 = 24 MHz clock must be divided by 12
329 AT91C_BASE_SSC->SSC_CMR = 12;
330
331 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
332 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
333 AT91C_BASE_SSC->SSC_TCMR = 0;
334 AT91C_BASE_SSC->SSC_TFMR = 0;
335
336 LED_D_ON();
337
338 // modulate antenna
339 HIGH(GPIO_SSC_DOUT);
340
341 // Charge TI tag for 50ms.
342 SpinDelay(50);
343
344 // stop modulating antenna and listen
345 LOW(GPIO_SSC_DOUT);
346
347 LED_D_OFF();
348
349 i = 0;
350 for(;;) {
351 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
352 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
353 i++; if(i >= TIBUFLEN) break;
354 }
355 WDT_HIT();
356 }
357
358 // return stolen pin to SSP
359 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
360 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
361
362 char *dest = (char *)BigBuf;
363 n = TIBUFLEN*32;
364 // unpack buffer
365 for (i=TIBUFLEN-1; i>=0; i--) {
366 for (j=0; j<32; j++) {
367 if(BigBuf[i] & (1 << j)) {
368 dest[--n] = 1;
369 } else {
370 dest[--n] = -1;
371 }
372 }
373 }
374 }
375
376 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
377 // if crc provided, it will be written with the data verbatim (even if bogus)
378 // if not provided a valid crc will be computed from the data and written.
379 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
380 {
381 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
382 if(crc == 0) {
383 crc = update_crc16(crc, (idlo)&0xff);
384 crc = update_crc16(crc, (idlo>>8)&0xff);
385 crc = update_crc16(crc, (idlo>>16)&0xff);
386 crc = update_crc16(crc, (idlo>>24)&0xff);
387 crc = update_crc16(crc, (idhi)&0xff);
388 crc = update_crc16(crc, (idhi>>8)&0xff);
389 crc = update_crc16(crc, (idhi>>16)&0xff);
390 crc = update_crc16(crc, (idhi>>24)&0xff);
391 }
392 Dbprintf("Writing to tag: %x%08x, crc=%x",
393 (unsigned int) idhi, (unsigned int) idlo, crc);
394
395 // TI tags charge at 134.2Khz
396 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
397 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
398 // connects to SSP_DIN and the SSP_DOUT logic level controls
399 // whether we're modulating the antenna (high)
400 // or listening to the antenna (low)
401 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
402 LED_A_ON();
403
404 // steal this pin from the SSP and use it to control the modulation
405 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
406 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
407
408 // writing algorithm:
409 // a high bit consists of a field off for 1ms and field on for 1ms
410 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
411 // initiate a charge time of 50ms (field on) then immediately start writing bits
412 // start by writing 0xBB (keyword) and 0xEB (password)
413 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
414 // finally end with 0x0300 (write frame)
415 // all data is sent lsb firts
416 // finish with 15ms programming time
417
418 // modulate antenna
419 HIGH(GPIO_SSC_DOUT);
420 SpinDelay(50); // charge time
421
422 WriteTIbyte(0xbb); // keyword
423 WriteTIbyte(0xeb); // password
424 WriteTIbyte( (idlo )&0xff );
425 WriteTIbyte( (idlo>>8 )&0xff );
426 WriteTIbyte( (idlo>>16)&0xff );
427 WriteTIbyte( (idlo>>24)&0xff );
428 WriteTIbyte( (idhi )&0xff );
429 WriteTIbyte( (idhi>>8 )&0xff );
430 WriteTIbyte( (idhi>>16)&0xff );
431 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
432 WriteTIbyte( (crc )&0xff ); // crc lo
433 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
434 WriteTIbyte(0x00); // write frame lo
435 WriteTIbyte(0x03); // write frame hi
436 HIGH(GPIO_SSC_DOUT);
437 SpinDelay(50); // programming time
438
439 LED_A_OFF();
440
441 // get TI tag data into the buffer
442 AcquireTiType();
443
444 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
445 DbpString("Now use tiread to check");
446 }
447
448 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
449 {
450 int i;
451 uint8_t *tab = (uint8_t *)BigBuf;
452
453 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
454 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
455
456 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
457
458 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
459 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
460
461 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
462 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
463
464 i = 0;
465 for(;;) {
466 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
467 if(BUTTON_PRESS()) {
468 DbpString("Stopped");
469 return;
470 }
471 WDT_HIT();
472 }
473
474 if (ledcontrol)
475 LED_D_ON();
476
477 if(tab[i])
478 OPEN_COIL();
479 else
480 SHORT_COIL();
481
482 if (ledcontrol)
483 LED_D_OFF();
484
485 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
486 if(BUTTON_PRESS()) {
487 DbpString("Stopped");
488 return;
489 }
490 WDT_HIT();
491 }
492
493 i++;
494 if(i == period) {
495 i = 0;
496 if (gap) {
497 SHORT_COIL();
498 SpinDelayUs(gap);
499 }
500 }
501 }
502 }
503
504 #define DEBUG_FRAME_CONTENTS 1
505 void SimulateTagLowFrequencyBidir(int divisor, int t0)
506 {
507 }
508
509 // compose fc/8 fc/10 waveform
510 static void fc(int c, int *n) {
511 uint8_t *dest = (uint8_t *)BigBuf;
512 int idx;
513
514 // for when we want an fc8 pattern every 4 logical bits
515 if(c==0) {
516 dest[((*n)++)]=1;
517 dest[((*n)++)]=1;
518 dest[((*n)++)]=0;
519 dest[((*n)++)]=0;
520 dest[((*n)++)]=0;
521 dest[((*n)++)]=0;
522 dest[((*n)++)]=0;
523 dest[((*n)++)]=0;
524 }
525 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
526 if(c==8) {
527 for (idx=0; idx<6; idx++) {
528 dest[((*n)++)]=1;
529 dest[((*n)++)]=1;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 dest[((*n)++)]=0;
536 }
537 }
538
539 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
540 if(c==10) {
541 for (idx=0; idx<5; idx++) {
542 dest[((*n)++)]=1;
543 dest[((*n)++)]=1;
544 dest[((*n)++)]=1;
545 dest[((*n)++)]=0;
546 dest[((*n)++)]=0;
547 dest[((*n)++)]=0;
548 dest[((*n)++)]=0;
549 dest[((*n)++)]=0;
550 dest[((*n)++)]=0;
551 dest[((*n)++)]=0;
552 }
553 }
554 }
555
556 // prepare a waveform pattern in the buffer based on the ID given then
557 // simulate a HID tag until the button is pressed
558 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
559 {
560 int n=0, i=0;
561 /*
562 HID tag bitstream format
563 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
564 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
565 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
566 A fc8 is inserted before every 4 bits
567 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
568 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
569 */
570
571 if (hi>0xFFF) {
572 DbpString("Tags can only have 44 bits.");
573 return;
574 }
575 fc(0,&n);
576 // special start of frame marker containing invalid bit sequences
577 fc(8, &n); fc(8, &n); // invalid
578 fc(8, &n); fc(10, &n); // logical 0
579 fc(10, &n); fc(10, &n); // invalid
580 fc(8, &n); fc(10, &n); // logical 0
581
582 WDT_HIT();
583 // manchester encode bits 43 to 32
584 for (i=11; i>=0; i--) {
585 if ((i%4)==3) fc(0,&n);
586 if ((hi>>i)&1) {
587 fc(10, &n); fc(8, &n); // low-high transition
588 } else {
589 fc(8, &n); fc(10, &n); // high-low transition
590 }
591 }
592
593 WDT_HIT();
594 // manchester encode bits 31 to 0
595 for (i=31; i>=0; i--) {
596 if ((i%4)==3) fc(0,&n);
597 if ((lo>>i)&1) {
598 fc(10, &n); fc(8, &n); // low-high transition
599 } else {
600 fc(8, &n); fc(10, &n); // high-low transition
601 }
602 }
603
604 if (ledcontrol)
605 LED_A_ON();
606 SimulateTagLowFrequency(n, 0, ledcontrol);
607
608 if (ledcontrol)
609 LED_A_OFF();
610 }
611
612
613 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
614 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
615 {
616 uint8_t *dest = (uint8_t *)BigBuf;
617 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
618 uint32_t hi2=0, hi=0, lo=0;
619
620 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
621 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
622 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
623
624 // Connect the A/D to the peak-detected low-frequency path.
625 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
626
627 // Give it a bit of time for the resonant antenna to settle.
628 SpinDelay(50);
629
630 // Now set up the SSC to get the ADC samples that are now streaming at us.
631 FpgaSetupSsc();
632
633 for(;;) {
634 WDT_HIT();
635 if (ledcontrol)
636 LED_A_ON();
637 if(BUTTON_PRESS()) {
638 DbpString("Stopped");
639 if (ledcontrol)
640 LED_A_OFF();
641 return;
642 }
643
644 i = 0;
645 m = sizeof(BigBuf);
646 memset(dest,128,m);
647 for(;;) {
648 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
649 AT91C_BASE_SSC->SSC_THR = 0x43;
650 if (ledcontrol)
651 LED_D_ON();
652 }
653 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
654 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
655 // we don't care about actual value, only if it's more or less than a
656 // threshold essentially we capture zero crossings for later analysis
657 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
658 i++;
659 if (ledcontrol)
660 LED_D_OFF();
661 if(i >= m) {
662 break;
663 }
664 }
665 }
666
667 // FSK demodulator
668
669 // sync to first lo-hi transition
670 for( idx=1; idx<m; idx++) {
671 if (dest[idx-1]<dest[idx])
672 lastval=idx;
673 break;
674 }
675 WDT_HIT();
676
677 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
678 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
679 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
680 for( i=0; idx<m; idx++) {
681 if (dest[idx-1]<dest[idx]) {
682 dest[i]=idx-lastval;
683 if (dest[i] <= 8) {
684 dest[i]=1;
685 } else {
686 dest[i]=0;
687 }
688
689 lastval=idx;
690 i++;
691 }
692 }
693 m=i;
694 WDT_HIT();
695
696 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
697 lastval=dest[0];
698 idx=0;
699 i=0;
700 n=0;
701 for( idx=0; idx<m; idx++) {
702 if (dest[idx]==lastval) {
703 n++;
704 } else {
705 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
706 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
707 // swallowed up by rounding
708 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
709 // special start of frame markers use invalid manchester states (no transitions) by using sequences
710 // like 111000
711 if (dest[idx-1]) {
712 n=(n+1)/6; // fc/8 in sets of 6
713 } else {
714 n=(n+1)/5; // fc/10 in sets of 5
715 }
716 switch (n) { // stuff appropriate bits in buffer
717 case 0:
718 case 1: // one bit
719 dest[i++]=dest[idx-1];
720 break;
721 case 2: // two bits
722 dest[i++]=dest[idx-1];
723 dest[i++]=dest[idx-1];
724 break;
725 case 3: // 3 bit start of frame markers
726 dest[i++]=dest[idx-1];
727 dest[i++]=dest[idx-1];
728 dest[i++]=dest[idx-1];
729 break;
730 // When a logic 0 is immediately followed by the start of the next transmisson
731 // (special pattern) a pattern of 4 bit duration lengths is created.
732 case 4:
733 dest[i++]=dest[idx-1];
734 dest[i++]=dest[idx-1];
735 dest[i++]=dest[idx-1];
736 dest[i++]=dest[idx-1];
737 break;
738 default: // this shouldn't happen, don't stuff any bits
739 break;
740 }
741 n=0;
742 lastval=dest[idx];
743 }
744 }
745 m=i;
746 WDT_HIT();
747
748 // final loop, go over previously decoded manchester data and decode into usable tag ID
749 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
750 for( idx=0; idx<m-6; idx++) {
751 // search for a start of frame marker
752 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
753 {
754 found=1;
755 idx+=6;
756 if (found && (hi2|hi|lo)) {
757 if (hi2 != 0){
758 Dbprintf("TAG ID: %x%08x%08x (%d)",
759 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
760 }
761 else {
762 Dbprintf("TAG ID: %x%08x (%d)",
763 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
764 }
765 /* if we're only looking for one tag */
766 if (findone)
767 {
768 *high = hi;
769 *low = lo;
770 return;
771 }
772 hi2=0;
773 hi=0;
774 lo=0;
775 found=0;
776 }
777 }
778 if (found) {
779 if (dest[idx] && (!dest[idx+1]) ) {
780 hi2=(hi2<<1)|(hi>>31);
781 hi=(hi<<1)|(lo>>31);
782 lo=(lo<<1)|0;
783 } else if ( (!dest[idx]) && dest[idx+1]) {
784 hi2=(hi2<<1)|(hi>>31);
785 hi=(hi<<1)|(lo>>31);
786 lo=(lo<<1)|1;
787 } else {
788 found=0;
789 hi2=0;
790 hi=0;
791 lo=0;
792 }
793 idx++;
794 }
795 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
796 {
797 found=1;
798 idx+=6;
799 if (found && (hi|lo)) {
800 if (hi2 != 0){
801 Dbprintf("TAG ID: %x%08x%08x (%d)",
802 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
803 }
804 else {
805 Dbprintf("TAG ID: %x%08x (%d)",
806 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
807 }
808 /* if we're only looking for one tag */
809 if (findone)
810 {
811 *high = hi;
812 *low = lo;
813 return;
814 }
815 hi2=0;
816 hi=0;
817 lo=0;
818 found=0;
819 }
820 }
821 }
822 WDT_HIT();
823 }
824 }
825
826 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
827 {
828 uint8_t *dest = (uint8_t *)BigBuf;
829 int m=0, n=0, i=0, idx=0, lastval=0;
830 int found=0;
831 uint32_t code=0, code2=0;
832 //uint32_t hi2=0, hi=0, lo=0;
833
834 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
835 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
836 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
837
838 // Connect the A/D to the peak-detected low-frequency path.
839 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
840
841 // Give it a bit of time for the resonant antenna to settle.
842 SpinDelay(50);
843
844 // Now set up the SSC to get the ADC samples that are now streaming at us.
845 FpgaSetupSsc();
846
847 for(;;) {
848 WDT_HIT();
849 if (ledcontrol)
850 LED_A_ON();
851 if(BUTTON_PRESS()) {
852 DbpString("Stopped");
853 if (ledcontrol)
854 LED_A_OFF();
855 return;
856 }
857
858 i = 0;
859 m = sizeof(BigBuf);
860 memset(dest,128,m);
861 for(;;) {
862 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
863 AT91C_BASE_SSC->SSC_THR = 0x43;
864 if (ledcontrol)
865 LED_D_ON();
866 }
867 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
868 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
869 // we don't care about actual value, only if it's more or less than a
870 // threshold essentially we capture zero crossings for later analysis
871 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
872 i++;
873 if (ledcontrol)
874 LED_D_OFF();
875 if(i >= m) {
876 break;
877 }
878 }
879 }
880
881 // FSK demodulator
882
883 // sync to first lo-hi transition
884 for( idx=1; idx<m; idx++) {
885 if (dest[idx-1]<dest[idx])
886 lastval=idx;
887 break;
888 }
889 WDT_HIT();
890
891 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
892 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
893 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
894 for( i=0; idx<m; idx++) {
895 if (dest[idx-1]<dest[idx]) {
896 dest[i]=idx-lastval;
897 if (dest[i] <= 8) {
898 dest[i]=1;
899 } else {
900 dest[i]=0;
901 }
902
903 lastval=idx;
904 i++;
905 }
906 }
907 m=i;
908 WDT_HIT();
909
910 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
911 lastval=dest[0];
912 idx=0;
913 i=0;
914 n=0;
915 for( idx=0; idx<m; idx++) {
916 if (dest[idx]==lastval) {
917 n++;
918 } else {
919 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
920 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
921 // swallowed up by rounding
922 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
923 // special start of frame markers use invalid manchester states (no transitions) by using sequences
924 // like 111000
925 if (dest[idx-1]) {
926 n=(n+1)/7; // fc/8 in sets of 7
927 } else {
928 n=(n+1)/6; // fc/10 in sets of 6
929 }
930 if (n < 13){
931 for(int j=0; j<n; j++){
932 dest[i++]=dest[idx-1]^1;
933 }
934 }
935 n=0;
936 lastval=dest[idx];
937 }
938 }//end for
939 m=i;
940 WDT_HIT();
941
942 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
943 for( idx=0; idx < m - 64; idx++) {
944
945 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
946 found=1;
947 m=idx;
948 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
949 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
950 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
951 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
952 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
953 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
954 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
955 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
956
957 short version='\x00';
958 char unknown='\x00';
959 uint16_t number=0;
960 for(int j=14;j<18;j++){
961 //Dbprintf("%d",dest[idx+j]);
962 version <<=1;
963 if (dest[idx+j]) version |= 1;
964 }
965 for(int j=18;j<26;j++){
966 //Dbprintf("%d",dest[idx+j]);
967 unknown <<=1;
968 if (dest[idx+j]) unknown |= 1;
969 }
970 for(int j=36;j<45;j++){
971 //Dbprintf("%d",dest[idx+j]);
972 number <<=1;
973 if (dest[idx+j]) number |= 1;
974 }
975 for(int j=46;j<53;j++){
976 //Dbprintf("%d",dest[idx+j]);
977 number <<=1;
978 if (dest[idx+j]) number |= 1;
979 }
980 for(int j=0; j<32; j++){
981 code <<=1;
982 if(dest[idx+j]) code |= 1;
983 }
984 for(int j=32; j<64; j++){
985 code2 <<=1;
986 if(dest[idx+j]) code2 |= 1;
987 }
988
989 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
990 if (ledcontrol)
991 LED_D_OFF();
992 }
993 // if we're only looking for one tag
994 if (found){
995 //*high = hi;
996 //*low = lo;
997 LED_A_OFF();
998 return;
999 }
1000
1001 found=0;
1002 }
1003 WDT_HIT();
1004 }
1005
1006 /*------------------------------
1007 * T5555/T5557/T5567 routines
1008 *------------------------------
1009 */
1010
1011 /* T55x7 configuration register definitions */
1012 #define T55x7_POR_DELAY 0x00000001
1013 #define T55x7_ST_TERMINATOR 0x00000008
1014 #define T55x7_PWD 0x00000010
1015 #define T55x7_MAXBLOCK_SHIFT 5
1016 #define T55x7_AOR 0x00000200
1017 #define T55x7_PSKCF_RF_2 0
1018 #define T55x7_PSKCF_RF_4 0x00000400
1019 #define T55x7_PSKCF_RF_8 0x00000800
1020 #define T55x7_MODULATION_DIRECT 0
1021 #define T55x7_MODULATION_PSK1 0x00001000
1022 #define T55x7_MODULATION_PSK2 0x00002000
1023 #define T55x7_MODULATION_PSK3 0x00003000
1024 #define T55x7_MODULATION_FSK1 0x00004000
1025 #define T55x7_MODULATION_FSK2 0x00005000
1026 #define T55x7_MODULATION_FSK1a 0x00006000
1027 #define T55x7_MODULATION_FSK2a 0x00007000
1028 #define T55x7_MODULATION_MANCHESTER 0x00008000
1029 #define T55x7_MODULATION_BIPHASE 0x00010000
1030 #define T55x7_BITRATE_RF_8 0
1031 #define T55x7_BITRATE_RF_16 0x00040000
1032 #define T55x7_BITRATE_RF_32 0x00080000
1033 #define T55x7_BITRATE_RF_40 0x000C0000
1034 #define T55x7_BITRATE_RF_50 0x00100000
1035 #define T55x7_BITRATE_RF_64 0x00140000
1036 #define T55x7_BITRATE_RF_100 0x00180000
1037 #define T55x7_BITRATE_RF_128 0x001C0000
1038
1039 /* T5555 (Q5) configuration register definitions */
1040 #define T5555_ST_TERMINATOR 0x00000001
1041 #define T5555_MAXBLOCK_SHIFT 0x00000001
1042 #define T5555_MODULATION_MANCHESTER 0
1043 #define T5555_MODULATION_PSK1 0x00000010
1044 #define T5555_MODULATION_PSK2 0x00000020
1045 #define T5555_MODULATION_PSK3 0x00000030
1046 #define T5555_MODULATION_FSK1 0x00000040
1047 #define T5555_MODULATION_FSK2 0x00000050
1048 #define T5555_MODULATION_BIPHASE 0x00000060
1049 #define T5555_MODULATION_DIRECT 0x00000070
1050 #define T5555_INVERT_OUTPUT 0x00000080
1051 #define T5555_PSK_RF_2 0
1052 #define T5555_PSK_RF_4 0x00000100
1053 #define T5555_PSK_RF_8 0x00000200
1054 #define T5555_USE_PWD 0x00000400
1055 #define T5555_USE_AOR 0x00000800
1056 #define T5555_BITRATE_SHIFT 12
1057 #define T5555_FAST_WRITE 0x00004000
1058 #define T5555_PAGE_SELECT 0x00008000
1059
1060 /*
1061 * Relevant times in microsecond
1062 * To compensate antenna falling times shorten the write times
1063 * and enlarge the gap ones.
1064 */
1065 #define START_GAP 250
1066 #define WRITE_GAP 160
1067 #define WRITE_0 144 // 192
1068 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
1069
1070 // Write one bit to card
1071 void T55xxWriteBit(int bit)
1072 {
1073 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1074 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1075 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1076 if (bit == 0)
1077 SpinDelayUs(WRITE_0);
1078 else
1079 SpinDelayUs(WRITE_1);
1080 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1081 SpinDelayUs(WRITE_GAP);
1082 }
1083
1084 // Write one card block in page 0, no lock
1085 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1086 {
1087 unsigned int i;
1088
1089 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1090 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1091 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1092
1093 // Give it a bit of time for the resonant antenna to settle.
1094 // And for the tag to fully power up
1095 SpinDelay(150);
1096
1097 // Now start writting
1098 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1099 SpinDelayUs(START_GAP);
1100
1101 // Opcode
1102 T55xxWriteBit(1);
1103 T55xxWriteBit(0); //Page 0
1104 if (PwdMode == 1){
1105 // Pwd
1106 for (i = 0x80000000; i != 0; i >>= 1)
1107 T55xxWriteBit(Pwd & i);
1108 }
1109 // Lock bit
1110 T55xxWriteBit(0);
1111
1112 // Data
1113 for (i = 0x80000000; i != 0; i >>= 1)
1114 T55xxWriteBit(Data & i);
1115
1116 // Block
1117 for (i = 0x04; i != 0; i >>= 1)
1118 T55xxWriteBit(Block & i);
1119
1120 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1121 // so wait a little more)
1122 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1123 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1124 SpinDelay(20);
1125 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1126 }
1127
1128 // Read one card block in page 0
1129 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1130 {
1131 uint8_t *dest = (uint8_t *)BigBuf;
1132 int m=0, i=0;
1133
1134 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1135 m = sizeof(BigBuf);
1136 // Clear destination buffer before sending the command
1137 memset(dest, 128, m);
1138 // Connect the A/D to the peak-detected low-frequency path.
1139 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1140 // Now set up the SSC to get the ADC samples that are now streaming at us.
1141 FpgaSetupSsc();
1142
1143 LED_D_ON();
1144 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1145 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1146
1147 // Give it a bit of time for the resonant antenna to settle.
1148 // And for the tag to fully power up
1149 SpinDelay(150);
1150
1151 // Now start writting
1152 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1153 SpinDelayUs(START_GAP);
1154
1155 // Opcode
1156 T55xxWriteBit(1);
1157 T55xxWriteBit(0); //Page 0
1158 if (PwdMode == 1){
1159 // Pwd
1160 for (i = 0x80000000; i != 0; i >>= 1)
1161 T55xxWriteBit(Pwd & i);
1162 }
1163 // Lock bit
1164 T55xxWriteBit(0);
1165 // Block
1166 for (i = 0x04; i != 0; i >>= 1)
1167 T55xxWriteBit(Block & i);
1168
1169 // Turn field on to read the response
1170 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1171 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1172
1173 // Now do the acquisition
1174 i = 0;
1175 for(;;) {
1176 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1177 AT91C_BASE_SSC->SSC_THR = 0x43;
1178 }
1179 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1180 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1181 // we don't care about actual value, only if it's more or less than a
1182 // threshold essentially we capture zero crossings for later analysis
1183 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1184 i++;
1185 if (i >= m) break;
1186 }
1187 }
1188
1189 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1190 LED_D_OFF();
1191 DbpString("DONE!");
1192 }
1193
1194 // Read card traceability data (page 1)
1195 void T55xxReadTrace(void){
1196 uint8_t *dest = (uint8_t *)BigBuf;
1197 int m=0, i=0;
1198
1199 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1200 m = sizeof(BigBuf);
1201 // Clear destination buffer before sending the command
1202 memset(dest, 128, m);
1203 // Connect the A/D to the peak-detected low-frequency path.
1204 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1205 // Now set up the SSC to get the ADC samples that are now streaming at us.
1206 FpgaSetupSsc();
1207
1208 LED_D_ON();
1209 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1210 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1211
1212 // Give it a bit of time for the resonant antenna to settle.
1213 // And for the tag to fully power up
1214 SpinDelay(150);
1215
1216 // Now start writting
1217 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1218 SpinDelayUs(START_GAP);
1219
1220 // Opcode
1221 T55xxWriteBit(1);
1222 T55xxWriteBit(1); //Page 1
1223
1224 // Turn field on to read the response
1225 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1226 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1227
1228 // Now do the acquisition
1229 i = 0;
1230 for(;;) {
1231 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1232 AT91C_BASE_SSC->SSC_THR = 0x43;
1233 }
1234 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1235 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1236 i++;
1237 if (i >= m) break;
1238 }
1239 }
1240
1241 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1242 LED_D_OFF();
1243 DbpString("DONE!");
1244 }
1245
1246 /*-------------- Cloning routines -----------*/
1247 // Copy HID id to card and setup block 0 config
1248 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1249 {
1250 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1251 int last_block = 0;
1252
1253 if (longFMT){
1254 // Ensure no more than 84 bits supplied
1255 if (hi2>0xFFFFF) {
1256 DbpString("Tags can only have 84 bits.");
1257 return;
1258 }
1259 // Build the 6 data blocks for supplied 84bit ID
1260 last_block = 6;
1261 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1262 for (int i=0;i<4;i++) {
1263 if (hi2 & (1<<(19-i)))
1264 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1265 else
1266 data1 |= (1<<((3-i)*2)); // 0 -> 01
1267 }
1268
1269 data2 = 0;
1270 for (int i=0;i<16;i++) {
1271 if (hi2 & (1<<(15-i)))
1272 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1273 else
1274 data2 |= (1<<((15-i)*2)); // 0 -> 01
1275 }
1276
1277 data3 = 0;
1278 for (int i=0;i<16;i++) {
1279 if (hi & (1<<(31-i)))
1280 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1281 else
1282 data3 |= (1<<((15-i)*2)); // 0 -> 01
1283 }
1284
1285 data4 = 0;
1286 for (int i=0;i<16;i++) {
1287 if (hi & (1<<(15-i)))
1288 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1289 else
1290 data4 |= (1<<((15-i)*2)); // 0 -> 01
1291 }
1292
1293 data5 = 0;
1294 for (int i=0;i<16;i++) {
1295 if (lo & (1<<(31-i)))
1296 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1297 else
1298 data5 |= (1<<((15-i)*2)); // 0 -> 01
1299 }
1300
1301 data6 = 0;
1302 for (int i=0;i<16;i++) {
1303 if (lo & (1<<(15-i)))
1304 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1305 else
1306 data6 |= (1<<((15-i)*2)); // 0 -> 01
1307 }
1308 }
1309 else {
1310 // Ensure no more than 44 bits supplied
1311 if (hi>0xFFF) {
1312 DbpString("Tags can only have 44 bits.");
1313 return;
1314 }
1315
1316 // Build the 3 data blocks for supplied 44bit ID
1317 last_block = 3;
1318
1319 data1 = 0x1D000000; // load preamble
1320
1321 for (int i=0;i<12;i++) {
1322 if (hi & (1<<(11-i)))
1323 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1324 else
1325 data1 |= (1<<((11-i)*2)); // 0 -> 01
1326 }
1327
1328 data2 = 0;
1329 for (int i=0;i<16;i++) {
1330 if (lo & (1<<(31-i)))
1331 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1332 else
1333 data2 |= (1<<((15-i)*2)); // 0 -> 01
1334 }
1335
1336 data3 = 0;
1337 for (int i=0;i<16;i++) {
1338 if (lo & (1<<(15-i)))
1339 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1340 else
1341 data3 |= (1<<((15-i)*2)); // 0 -> 01
1342 }
1343 }
1344
1345 LED_D_ON();
1346 // Program the data blocks for supplied ID
1347 // and the block 0 for HID format
1348 T55xxWriteBlock(data1,1,0,0);
1349 T55xxWriteBlock(data2,2,0,0);
1350 T55xxWriteBlock(data3,3,0,0);
1351
1352 if (longFMT) { // if long format there are 6 blocks
1353 T55xxWriteBlock(data4,4,0,0);
1354 T55xxWriteBlock(data5,5,0,0);
1355 T55xxWriteBlock(data6,6,0,0);
1356 }
1357
1358 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1359 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1360 T55x7_MODULATION_FSK2a |
1361 last_block << T55x7_MAXBLOCK_SHIFT,
1362 0,0,0);
1363
1364 LED_D_OFF();
1365
1366 DbpString("DONE!");
1367 }
1368
1369 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1370 {
1371 int data1=0, data2=0; //up to six blocks for long format
1372
1373 data1 = hi; // load preamble
1374 data2 = lo;
1375
1376 LED_D_ON();
1377 // Program the data blocks for supplied ID
1378 // and the block 0 for HID format
1379 T55xxWriteBlock(data1,1,0,0);
1380 T55xxWriteBlock(data2,2,0,0);
1381
1382 //Config Block
1383 T55xxWriteBlock(0x00147040,0,0,0);
1384 LED_D_OFF();
1385
1386 DbpString("DONE!");
1387 }
1388
1389 // Define 9bit header for EM410x tags
1390 #define EM410X_HEADER 0x1FF
1391 #define EM410X_ID_LENGTH 40
1392
1393 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1394 {
1395 int i, id_bit;
1396 uint64_t id = EM410X_HEADER;
1397 uint64_t rev_id = 0; // reversed ID
1398 int c_parity[4]; // column parity
1399 int r_parity = 0; // row parity
1400 uint32_t clock = 0;
1401
1402 // Reverse ID bits given as parameter (for simpler operations)
1403 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1404 if (i < 32) {
1405 rev_id = (rev_id << 1) | (id_lo & 1);
1406 id_lo >>= 1;
1407 } else {
1408 rev_id = (rev_id << 1) | (id_hi & 1);
1409 id_hi >>= 1;
1410 }
1411 }
1412
1413 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1414 id_bit = rev_id & 1;
1415
1416 if (i % 4 == 0) {
1417 // Don't write row parity bit at start of parsing
1418 if (i)
1419 id = (id << 1) | r_parity;
1420 // Start counting parity for new row
1421 r_parity = id_bit;
1422 } else {
1423 // Count row parity
1424 r_parity ^= id_bit;
1425 }
1426
1427 // First elements in column?
1428 if (i < 4)
1429 // Fill out first elements
1430 c_parity[i] = id_bit;
1431 else
1432 // Count column parity
1433 c_parity[i % 4] ^= id_bit;
1434
1435 // Insert ID bit
1436 id = (id << 1) | id_bit;
1437 rev_id >>= 1;
1438 }
1439
1440 // Insert parity bit of last row
1441 id = (id << 1) | r_parity;
1442
1443 // Fill out column parity at the end of tag
1444 for (i = 0; i < 4; ++i)
1445 id = (id << 1) | c_parity[i];
1446
1447 // Add stop bit
1448 id <<= 1;
1449
1450 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1451 LED_D_ON();
1452
1453 // Write EM410x ID
1454 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1455 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1456
1457 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1458 if (card) {
1459 // Clock rate is stored in bits 8-15 of the card value
1460 clock = (card & 0xFF00) >> 8;
1461 Dbprintf("Clock rate: %d", clock);
1462 switch (clock)
1463 {
1464 case 32:
1465 clock = T55x7_BITRATE_RF_32;
1466 break;
1467 case 16:
1468 clock = T55x7_BITRATE_RF_16;
1469 break;
1470 case 0:
1471 // A value of 0 is assumed to be 64 for backwards-compatibility
1472 // Fall through...
1473 case 64:
1474 clock = T55x7_BITRATE_RF_64;
1475 break;
1476 default:
1477 Dbprintf("Invalid clock rate: %d", clock);
1478 return;
1479 }
1480
1481 // Writing configuration for T55x7 tag
1482 T55xxWriteBlock(clock |
1483 T55x7_MODULATION_MANCHESTER |
1484 2 << T55x7_MAXBLOCK_SHIFT,
1485 0, 0, 0);
1486 }
1487 else
1488 // Writing configuration for T5555(Q5) tag
1489 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1490 T5555_MODULATION_MANCHESTER |
1491 2 << T5555_MAXBLOCK_SHIFT,
1492 0, 0, 0);
1493
1494 LED_D_OFF();
1495 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1496 (uint32_t)(id >> 32), (uint32_t)id);
1497 }
1498
1499 // Clone Indala 64-bit tag by UID to T55x7
1500 void CopyIndala64toT55x7(int hi, int lo)
1501 {
1502
1503 //Program the 2 data blocks for supplied 64bit UID
1504 // and the block 0 for Indala64 format
1505 T55xxWriteBlock(hi,1,0,0);
1506 T55xxWriteBlock(lo,2,0,0);
1507 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1508 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1509 T55x7_MODULATION_PSK1 |
1510 2 << T55x7_MAXBLOCK_SHIFT,
1511 0, 0, 0);
1512 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1513 // T5567WriteBlock(0x603E1042,0);
1514
1515 DbpString("DONE!");
1516
1517 }
1518
1519 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1520 {
1521
1522 //Program the 7 data blocks for supplied 224bit UID
1523 // and the block 0 for Indala224 format
1524 T55xxWriteBlock(uid1,1,0,0);
1525 T55xxWriteBlock(uid2,2,0,0);
1526 T55xxWriteBlock(uid3,3,0,0);
1527 T55xxWriteBlock(uid4,4,0,0);
1528 T55xxWriteBlock(uid5,5,0,0);
1529 T55xxWriteBlock(uid6,6,0,0);
1530 T55xxWriteBlock(uid7,7,0,0);
1531 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1532 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1533 T55x7_MODULATION_PSK1 |
1534 7 << T55x7_MAXBLOCK_SHIFT,
1535 0,0,0);
1536 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1537 // T5567WriteBlock(0x603E10E2,0);
1538
1539 DbpString("DONE!");
1540
1541 }
1542
1543
1544 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1545 #define max(x,y) ( x<y ? y:x)
1546
1547 int DemodPCF7931(uint8_t **outBlocks) {
1548 uint8_t BitStream[256];
1549 uint8_t Blocks[8][16];
1550 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1551 int GraphTraceLen = sizeof(BigBuf);
1552 int i, j, lastval, bitidx, half_switch;
1553 int clock = 64;
1554 int tolerance = clock / 8;
1555 int pmc, block_done;
1556 int lc, warnings = 0;
1557 int num_blocks = 0;
1558 int lmin=128, lmax=128;
1559 uint8_t dir;
1560
1561 AcquireRawAdcSamples125k(0);
1562
1563 lmin = 64;
1564 lmax = 192;
1565
1566 i = 2;
1567
1568 /* Find first local max/min */
1569 if(GraphBuffer[1] > GraphBuffer[0]) {
1570 while(i < GraphTraceLen) {
1571 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1572 break;
1573 i++;
1574 }
1575 dir = 0;
1576 }
1577 else {
1578 while(i < GraphTraceLen) {
1579 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1580 break;
1581 i++;
1582 }
1583 dir = 1;
1584 }
1585
1586 lastval = i++;
1587 half_switch = 0;
1588 pmc = 0;
1589 block_done = 0;
1590
1591 for (bitidx = 0; i < GraphTraceLen; i++)
1592 {
1593 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1594 {
1595 lc = i - lastval;
1596 lastval = i;
1597
1598 // Switch depending on lc length:
1599 // Tolerance is 1/8 of clock rate (arbitrary)
1600 if (abs(lc-clock/4) < tolerance) {
1601 // 16T0
1602 if((i - pmc) == lc) { /* 16T0 was previous one */
1603 /* It's a PMC ! */
1604 i += (128+127+16+32+33+16)-1;
1605 lastval = i;
1606 pmc = 0;
1607 block_done = 1;
1608 }
1609 else {
1610 pmc = i;
1611 }
1612 } else if (abs(lc-clock/2) < tolerance) {
1613 // 32TO
1614 if((i - pmc) == lc) { /* 16T0 was previous one */
1615 /* It's a PMC ! */
1616 i += (128+127+16+32+33)-1;
1617 lastval = i;
1618 pmc = 0;
1619 block_done = 1;
1620 }
1621 else if(half_switch == 1) {
1622 BitStream[bitidx++] = 0;
1623 half_switch = 0;
1624 }
1625 else
1626 half_switch++;
1627 } else if (abs(lc-clock) < tolerance) {
1628 // 64TO
1629 BitStream[bitidx++] = 1;
1630 } else {
1631 // Error
1632 warnings++;
1633 if (warnings > 10)
1634 {
1635 Dbprintf("Error: too many detection errors, aborting.");
1636 return 0;
1637 }
1638 }
1639
1640 if(block_done == 1) {
1641 if(bitidx == 128) {
1642 for(j=0; j<16; j++) {
1643 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1644 64*BitStream[j*8+6]+
1645 32*BitStream[j*8+5]+
1646 16*BitStream[j*8+4]+
1647 8*BitStream[j*8+3]+
1648 4*BitStream[j*8+2]+
1649 2*BitStream[j*8+1]+
1650 BitStream[j*8];
1651 }
1652 num_blocks++;
1653 }
1654 bitidx = 0;
1655 block_done = 0;
1656 half_switch = 0;
1657 }
1658 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1659 else dir = 1;
1660 }
1661 if(bitidx==255)
1662 bitidx=0;
1663 warnings = 0;
1664 if(num_blocks == 4) break;
1665 }
1666 memcpy(outBlocks, Blocks, 16*num_blocks);
1667 return num_blocks;
1668 }
1669
1670 int IsBlock0PCF7931(uint8_t *Block) {
1671 // Assume RFU means 0 :)
1672 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1673 return 1;
1674 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1675 return 1;
1676 return 0;
1677 }
1678
1679 int IsBlock1PCF7931(uint8_t *Block) {
1680 // Assume RFU means 0 :)
1681 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1682 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1683 return 1;
1684
1685 return 0;
1686 }
1687
1688 #define ALLOC 16
1689
1690 void ReadPCF7931() {
1691 uint8_t Blocks[8][17];
1692 uint8_t tmpBlocks[4][16];
1693 int i, j, ind, ind2, n;
1694 int num_blocks = 0;
1695 int max_blocks = 8;
1696 int ident = 0;
1697 int error = 0;
1698 int tries = 0;
1699
1700 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1701
1702 do {
1703 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1704 n = DemodPCF7931((uint8_t**)tmpBlocks);
1705 if(!n)
1706 error++;
1707 if(error==10 && num_blocks == 0) {
1708 Dbprintf("Error, no tag or bad tag");
1709 return;
1710 }
1711 else if (tries==20 || error==10) {
1712 Dbprintf("Error reading the tag");
1713 Dbprintf("Here is the partial content");
1714 goto end;
1715 }
1716
1717 for(i=0; i<n; i++)
1718 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1719 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1720 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1721 if(!ident) {
1722 for(i=0; i<n; i++) {
1723 if(IsBlock0PCF7931(tmpBlocks[i])) {
1724 // Found block 0 ?
1725 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1726 // Found block 1!
1727 // \o/
1728 ident = 1;
1729 memcpy(Blocks[0], tmpBlocks[i], 16);
1730 Blocks[0][ALLOC] = 1;
1731 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1732 Blocks[1][ALLOC] = 1;
1733 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1734 // Debug print
1735 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1736 num_blocks = 2;
1737 // Handle following blocks
1738 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1739 if(j==n) j=0;
1740 if(j==i) break;
1741 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1742 Blocks[ind2][ALLOC] = 1;
1743 }
1744 break;
1745 }
1746 }
1747 }
1748 }
1749 else {
1750 for(i=0; i<n; i++) { // Look for identical block in known blocks
1751 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1752 for(j=0; j<max_blocks; j++) {
1753 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1754 // Found an identical block
1755 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1756 if(ind2 < 0)
1757 ind2 = max_blocks;
1758 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1759 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1760 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1761 Blocks[ind2][ALLOC] = 1;
1762 num_blocks++;
1763 if(num_blocks == max_blocks) goto end;
1764 }
1765 }
1766 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1767 if(ind2 > max_blocks)
1768 ind2 = 0;
1769 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1770 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1771 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1772 Blocks[ind2][ALLOC] = 1;
1773 num_blocks++;
1774 if(num_blocks == max_blocks) goto end;
1775 }
1776 }
1777 }
1778 }
1779 }
1780 }
1781 }
1782 tries++;
1783 if (BUTTON_PRESS()) return;
1784 } while (num_blocks != max_blocks);
1785 end:
1786 Dbprintf("-----------------------------------------");
1787 Dbprintf("Memory content:");
1788 Dbprintf("-----------------------------------------");
1789 for(i=0; i<max_blocks; i++) {
1790 if(Blocks[i][ALLOC]==1)
1791 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1792 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1793 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1794 else
1795 Dbprintf("<missing block %d>", i);
1796 }
1797 Dbprintf("-----------------------------------------");
1798
1799 return ;
1800 }
1801
1802
1803 //-----------------------------------
1804 // EM4469 / EM4305 routines
1805 //-----------------------------------
1806 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1807 #define FWD_CMD_WRITE 0xA
1808 #define FWD_CMD_READ 0x9
1809 #define FWD_CMD_DISABLE 0x5
1810
1811
1812 uint8_t forwardLink_data[64]; //array of forwarded bits
1813 uint8_t * forward_ptr; //ptr for forward message preparation
1814 uint8_t fwd_bit_sz; //forwardlink bit counter
1815 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1816
1817 //====================================================================
1818 // prepares command bits
1819 // see EM4469 spec
1820 //====================================================================
1821 //--------------------------------------------------------------------
1822 uint8_t Prepare_Cmd( uint8_t cmd ) {
1823 //--------------------------------------------------------------------
1824
1825 *forward_ptr++ = 0; //start bit
1826 *forward_ptr++ = 0; //second pause for 4050 code
1827
1828 *forward_ptr++ = cmd;
1829 cmd >>= 1;
1830 *forward_ptr++ = cmd;
1831 cmd >>= 1;
1832 *forward_ptr++ = cmd;
1833 cmd >>= 1;
1834 *forward_ptr++ = cmd;
1835
1836 return 6; //return number of emited bits
1837 }
1838
1839 //====================================================================
1840 // prepares address bits
1841 // see EM4469 spec
1842 //====================================================================
1843
1844 //--------------------------------------------------------------------
1845 uint8_t Prepare_Addr( uint8_t addr ) {
1846 //--------------------------------------------------------------------
1847
1848 register uint8_t line_parity;
1849
1850 uint8_t i;
1851 line_parity = 0;
1852 for(i=0;i<6;i++) {
1853 *forward_ptr++ = addr;
1854 line_parity ^= addr;
1855 addr >>= 1;
1856 }
1857
1858 *forward_ptr++ = (line_parity & 1);
1859
1860 return 7; //return number of emited bits
1861 }
1862
1863 //====================================================================
1864 // prepares data bits intreleaved with parity bits
1865 // see EM4469 spec
1866 //====================================================================
1867
1868 //--------------------------------------------------------------------
1869 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1870 //--------------------------------------------------------------------
1871
1872 register uint8_t line_parity;
1873 register uint8_t column_parity;
1874 register uint8_t i, j;
1875 register uint16_t data;
1876
1877 data = data_low;
1878 column_parity = 0;
1879
1880 for(i=0; i<4; i++) {
1881 line_parity = 0;
1882 for(j=0; j<8; j++) {
1883 line_parity ^= data;
1884 column_parity ^= (data & 1) << j;
1885 *forward_ptr++ = data;
1886 data >>= 1;
1887 }
1888 *forward_ptr++ = line_parity;
1889 if(i == 1)
1890 data = data_hi;
1891 }
1892
1893 for(j=0; j<8; j++) {
1894 *forward_ptr++ = column_parity;
1895 column_parity >>= 1;
1896 }
1897 *forward_ptr = 0;
1898
1899 return 45; //return number of emited bits
1900 }
1901
1902 //====================================================================
1903 // Forward Link send function
1904 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1905 // fwd_bit_count set with number of bits to be sent
1906 //====================================================================
1907 void SendForward(uint8_t fwd_bit_count) {
1908
1909 fwd_write_ptr = forwardLink_data;
1910 fwd_bit_sz = fwd_bit_count;
1911
1912 LED_D_ON();
1913
1914 //Field on
1915 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1916 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1917 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1918
1919 // Give it a bit of time for the resonant antenna to settle.
1920 // And for the tag to fully power up
1921 SpinDelay(150);
1922
1923 // force 1st mod pulse (start gap must be longer for 4305)
1924 fwd_bit_sz--; //prepare next bit modulation
1925 fwd_write_ptr++;
1926 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1927 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1928 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1929 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1930 SpinDelayUs(16*8); //16 cycles on (8us each)
1931
1932 // now start writting
1933 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1934 if(((*fwd_write_ptr++) & 1) == 1)
1935 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1936 else {
1937 //These timings work for 4469/4269/4305 (with the 55*8 above)
1938 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1939 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1940 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1941 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1942 SpinDelayUs(9*8); //16 cycles on (8us each)
1943 }
1944 }
1945 }
1946
1947 void EM4xLogin(uint32_t Password) {
1948
1949 uint8_t fwd_bit_count;
1950
1951 forward_ptr = forwardLink_data;
1952 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1953 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1954
1955 SendForward(fwd_bit_count);
1956
1957 //Wait for command to complete
1958 SpinDelay(20);
1959
1960 }
1961
1962 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1963
1964 uint8_t fwd_bit_count;
1965 uint8_t *dest = (uint8_t *)BigBuf;
1966 int m=0, i=0;
1967
1968 //If password mode do login
1969 if (PwdMode == 1) EM4xLogin(Pwd);
1970
1971 forward_ptr = forwardLink_data;
1972 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1973 fwd_bit_count += Prepare_Addr( Address );
1974
1975 m = sizeof(BigBuf);
1976 // Clear destination buffer before sending the command
1977 memset(dest, 128, m);
1978 // Connect the A/D to the peak-detected low-frequency path.
1979 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1980 // Now set up the SSC to get the ADC samples that are now streaming at us.
1981 FpgaSetupSsc();
1982
1983 SendForward(fwd_bit_count);
1984
1985 // Now do the acquisition
1986 i = 0;
1987 for(;;) {
1988 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1989 AT91C_BASE_SSC->SSC_THR = 0x43;
1990 }
1991 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1992 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1993 i++;
1994 if (i >= m) break;
1995 }
1996 }
1997 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1998 LED_D_OFF();
1999 }
2000
2001 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2002
2003 uint8_t fwd_bit_count;
2004
2005 //If password mode do login
2006 if (PwdMode == 1) EM4xLogin(Pwd);
2007
2008 forward_ptr = forwardLink_data;
2009 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2010 fwd_bit_count += Prepare_Addr( Address );
2011 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2012
2013 SendForward(fwd_bit_count);
2014
2015 //Wait for write to complete
2016 SpinDelay(20);
2017 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2018 LED_D_OFF();
2019 }
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