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Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19
20
21 /**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29 {
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73 }
74
75
76
77 /* blank r/w tag data stream
78 ...0000000000000000 01111111
79 1010101010101010101010101010101010101010101010101010101010101010
80 0011010010100001
81 01111111
82 101010101010101[0]000...
83
84 [5555fe852c5555555555555555fe0000]
85 */
86 void ReadTItag(void)
87 {
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
179 if (shift3 & (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214 }
215
216 void WriteTIbyte(uint8_t b)
217 {
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239 }
240
241 void AcquireTiType(void)
242 {
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN*32;
300 // unpack buffer
301 for (i=TIBUFLEN-1; i>=0; i--) {
302 for (j=0; j<32; j++) {
303 if(BigBuf[i] & (1 << j)) {
304 dest[--n] = 1;
305 } else {
306 dest[--n] = -1;
307 }
308 }
309 }
310 }
311
312 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313 // if crc provided, it will be written with the data verbatim (even if bogus)
314 // if not provided a valid crc will be computed from the data and written.
315 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
316 {
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
318 if(crc == 0) {
319 crc = update_crc16(crc, (idlo)&0xff);
320 crc = update_crc16(crc, (idlo>>8)&0xff);
321 crc = update_crc16(crc, (idlo>>16)&0xff);
322 crc = update_crc16(crc, (idlo>>24)&0xff);
323 crc = update_crc16(crc, (idhi)&0xff);
324 crc = update_crc16(crc, (idhi>>8)&0xff);
325 crc = update_crc16(crc, (idhi>>16)&0xff);
326 crc = update_crc16(crc, (idhi>>24)&0xff);
327 }
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use tiread to check");
382 }
383
384 void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
385 {
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS()) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409
410 if (ledcontrol)
411 LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol)
419 LED_D_OFF();
420
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if(BUTTON_PRESS()) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform
446 static void fc(int c, int *n) {
447 uint8_t *dest = BigBuf_get_addr();
448 int idx;
449
450 // for when we want an fc8 pattern every 4 logical bits
451 if(c==0) {
452 dest[((*n)++)]=1;
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=0;
455 dest[((*n)++)]=0;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 }
461 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
462 if(c==8) {
463 for (idx=0; idx<6; idx++) {
464 dest[((*n)++)]=1;
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=0;
467 dest[((*n)++)]=0;
468 dest[((*n)++)]=0;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 }
473 }
474
475 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
476 if(c==10) {
477 for (idx=0; idx<5; idx++) {
478 dest[((*n)++)]=1;
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=0;
482 dest[((*n)++)]=0;
483 dest[((*n)++)]=0;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 }
489 }
490 }
491
492 // prepare a waveform pattern in the buffer based on the ID given then
493 // simulate a HID tag until the button is pressed
494 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
495 {
496 int n=0, i=0;
497 /*
498 HID tag bitstream format
499 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
500 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
501 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
502 A fc8 is inserted before every 4 bits
503 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
504 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
505 */
506
507 if (hi>0xFFF) {
508 DbpString("Tags can only have 44 bits.");
509 return;
510 }
511 fc(0,&n);
512 // special start of frame marker containing invalid bit sequences
513 fc(8, &n); fc(8, &n); // invalid
514 fc(8, &n); fc(10, &n); // logical 0
515 fc(10, &n); fc(10, &n); // invalid
516 fc(8, &n); fc(10, &n); // logical 0
517
518 WDT_HIT();
519 // manchester encode bits 43 to 32
520 for (i=11; i>=0; i--) {
521 if ((i%4)==3) fc(0,&n);
522 if ((hi>>i)&1) {
523 fc(10, &n); fc(8, &n); // low-high transition
524 } else {
525 fc(8, &n); fc(10, &n); // high-low transition
526 }
527 }
528
529 WDT_HIT();
530 // manchester encode bits 31 to 0
531 for (i=31; i>=0; i--) {
532 if ((i%4)==3) fc(0,&n);
533 if ((lo>>i)&1) {
534 fc(10, &n); fc(8, &n); // low-high transition
535 } else {
536 fc(8, &n); fc(10, &n); // high-low transition
537 }
538 }
539
540 if (ledcontrol)
541 LED_A_ON();
542 SimulateTagLowFrequency(n, 0, ledcontrol);
543
544 if (ledcontrol)
545 LED_A_OFF();
546 }
547
548 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
549 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
550 {
551 uint8_t *dest = BigBuf_get_addr();
552 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
553 size_t size = 0;
554 uint32_t hi2=0, hi=0, lo=0;
555 int idx=0;
556 // Configure to go in 125Khz listen mode
557 LFSetupFPGAForADC(95, true);
558
559 while(!BUTTON_PRESS()) {
560
561 WDT_HIT();
562 if (ledcontrol) LED_A_ON();
563
564 DoAcquisition_default(-1,true);
565 // FSK demodulator
566 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
567 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
568
569 if (idx>0 && lo>0){
570 // final loop, go over previously decoded manchester data and decode into usable tag ID
571 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
572 if (hi2 != 0){ //extra large HID tags
573 Dbprintf("TAG ID: %x%08x%08x (%d)",
574 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
575 }else { //standard HID tags <38 bits
576 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
577 uint8_t bitlen = 0;
578 uint32_t fc = 0;
579 uint32_t cardnum = 0;
580 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
581 uint32_t lo2=0;
582 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
583 uint8_t idx3 = 1;
584 while(lo2 > 1){ //find last bit set to 1 (format len bit)
585 lo2=lo2 >> 1;
586 idx3++;
587 }
588 bitlen = idx3+19;
589 fc =0;
590 cardnum=0;
591 if(bitlen == 26){
592 cardnum = (lo>>1)&0xFFFF;
593 fc = (lo>>17)&0xFF;
594 }
595 if(bitlen == 37){
596 cardnum = (lo>>1)&0x7FFFF;
597 fc = ((hi&0xF)<<12)|(lo>>20);
598 }
599 if(bitlen == 34){
600 cardnum = (lo>>1)&0xFFFF;
601 fc= ((hi&1)<<15)|(lo>>17);
602 }
603 if(bitlen == 35){
604 cardnum = (lo>>1)&0xFFFFF;
605 fc = ((hi&1)<<11)|(lo>>21);
606 }
607 }
608 else { //if bit 38 is not set then 37 bit format is used
609 bitlen= 37;
610 fc =0;
611 cardnum=0;
612 if(bitlen==37){
613 cardnum = (lo>>1)&0x7FFFF;
614 fc = ((hi&0xF)<<12)|(lo>>20);
615 }
616 }
617 //Dbprintf("TAG ID: %x%08x (%d)",
618 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
619 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
620 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
621 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
622 }
623 if (findone){
624 if (ledcontrol) LED_A_OFF();
625 *high = hi;
626 *low = lo;
627 return;
628 }
629 // reset
630 hi2 = hi = lo = 0;
631 }
632 WDT_HIT();
633 }
634 DbpString("Stopped");
635 if (ledcontrol) LED_A_OFF();
636 }
637
638 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
639 {
640 uint8_t *dest = BigBuf_get_addr();
641
642 size_t size=0, idx=0;
643 int clk=0, invert=0, errCnt=0, maxErr=20;
644 uint64_t lo=0;
645 // Configure to go in 125Khz listen mode
646 LFSetupFPGAForADC(95, true);
647
648 while(!BUTTON_PRESS()) {
649
650 WDT_HIT();
651 if (ledcontrol) LED_A_ON();
652
653 DoAcquisition_default(-1,true);
654 size = BigBuf_max_traceLen();
655 //Dbprintf("DEBUG: Buffer got");
656 //askdemod and manchester decode
657 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
658 //Dbprintf("DEBUG: ASK Got");
659 WDT_HIT();
660
661 if (errCnt>=0){
662 lo = Em410xDecode(dest, &size, &idx);
663 //Dbprintf("DEBUG: EM GOT");
664 if (lo>0){
665 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
666 (uint32_t)(lo>>32),
667 (uint32_t)lo,
668 (uint32_t)(lo&0xFFFF),
669 (uint32_t)((lo>>16LL) & 0xFF),
670 (uint32_t)(lo & 0xFFFFFF));
671 }
672 if (findone){
673 if (ledcontrol) LED_A_OFF();
674 *high=lo>>32;
675 *low=lo & 0xFFFFFFFF;
676 return;
677 }
678 } else{
679 //Dbprintf("DEBUG: No Tag");
680 }
681 WDT_HIT();
682 lo = 0;
683 clk=0;
684 invert=0;
685 errCnt=0;
686 size=0;
687 }
688 DbpString("Stopped");
689 if (ledcontrol) LED_A_OFF();
690 }
691
692 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
693 {
694 uint8_t *dest = BigBuf_get_addr();
695 int idx=0;
696 uint32_t code=0, code2=0;
697 uint8_t version=0;
698 uint8_t facilitycode=0;
699 uint16_t number=0;
700 // Configure to go in 125Khz listen mode
701 LFSetupFPGAForADC(95, true);
702
703 while(!BUTTON_PRESS()) {
704 WDT_HIT();
705 if (ledcontrol) LED_A_ON();
706 DoAcquisition_default(-1,true);
707 //fskdemod and get start index
708 WDT_HIT();
709 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
710 if (idx>0){
711 //valid tag found
712
713 //Index map
714 //0 10 20 30 40 50 60
715 //| | | | | | |
716 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
717 //-----------------------------------------------------------------------------
718 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
719 //
720 //XSF(version)facility:codeone+codetwo
721 //Handle the data
722 if(findone){ //only print binary if we are doing one
723 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
724 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
725 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
726 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
727 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
728 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
729 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
730 }
731 code = bytebits_to_byte(dest+idx,32);
732 code2 = bytebits_to_byte(dest+idx+32,32);
733 version = bytebits_to_byte(dest+idx+27,8); //14,4
734 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
735 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
736
737 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
738 // if we're only looking for one tag
739 if (findone){
740 if (ledcontrol) LED_A_OFF();
741 //LED_A_OFF();
742 *high=code;
743 *low=code2;
744 return;
745 }
746 code=code2=0;
747 version=facilitycode=0;
748 number=0;
749 idx=0;
750 }
751 WDT_HIT();
752 }
753 DbpString("Stopped");
754 if (ledcontrol) LED_A_OFF();
755 }
756
757 /*------------------------------
758 * T5555/T5557/T5567 routines
759 *------------------------------
760 */
761
762 /* T55x7 configuration register definitions */
763 #define T55x7_POR_DELAY 0x00000001
764 #define T55x7_ST_TERMINATOR 0x00000008
765 #define T55x7_PWD 0x00000010
766 #define T55x7_MAXBLOCK_SHIFT 5
767 #define T55x7_AOR 0x00000200
768 #define T55x7_PSKCF_RF_2 0
769 #define T55x7_PSKCF_RF_4 0x00000400
770 #define T55x7_PSKCF_RF_8 0x00000800
771 #define T55x7_MODULATION_DIRECT 0
772 #define T55x7_MODULATION_PSK1 0x00001000
773 #define T55x7_MODULATION_PSK2 0x00002000
774 #define T55x7_MODULATION_PSK3 0x00003000
775 #define T55x7_MODULATION_FSK1 0x00004000
776 #define T55x7_MODULATION_FSK2 0x00005000
777 #define T55x7_MODULATION_FSK1a 0x00006000
778 #define T55x7_MODULATION_FSK2a 0x00007000
779 #define T55x7_MODULATION_MANCHESTER 0x00008000
780 #define T55x7_MODULATION_BIPHASE 0x00010000
781 #define T55x7_BITRATE_RF_8 0
782 #define T55x7_BITRATE_RF_16 0x00040000
783 #define T55x7_BITRATE_RF_32 0x00080000
784 #define T55x7_BITRATE_RF_40 0x000C0000
785 #define T55x7_BITRATE_RF_50 0x00100000
786 #define T55x7_BITRATE_RF_64 0x00140000
787 #define T55x7_BITRATE_RF_100 0x00180000
788 #define T55x7_BITRATE_RF_128 0x001C0000
789
790 /* T5555 (Q5) configuration register definitions */
791 #define T5555_ST_TERMINATOR 0x00000001
792 #define T5555_MAXBLOCK_SHIFT 0x00000001
793 #define T5555_MODULATION_MANCHESTER 0
794 #define T5555_MODULATION_PSK1 0x00000010
795 #define T5555_MODULATION_PSK2 0x00000020
796 #define T5555_MODULATION_PSK3 0x00000030
797 #define T5555_MODULATION_FSK1 0x00000040
798 #define T5555_MODULATION_FSK2 0x00000050
799 #define T5555_MODULATION_BIPHASE 0x00000060
800 #define T5555_MODULATION_DIRECT 0x00000070
801 #define T5555_INVERT_OUTPUT 0x00000080
802 #define T5555_PSK_RF_2 0
803 #define T5555_PSK_RF_4 0x00000100
804 #define T5555_PSK_RF_8 0x00000200
805 #define T5555_USE_PWD 0x00000400
806 #define T5555_USE_AOR 0x00000800
807 #define T5555_BITRATE_SHIFT 12
808 #define T5555_FAST_WRITE 0x00004000
809 #define T5555_PAGE_SELECT 0x00008000
810
811 /*
812 * Relevant times in microsecond
813 * To compensate antenna falling times shorten the write times
814 * and enlarge the gap ones.
815 */
816 #define START_GAP 30*8 // 10 - 50fc 250
817 #define WRITE_GAP 20*8 // 8 - 30fc
818 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
819 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
820
821 // VALUES TAKEN FROM EM4x function: SendForward
822 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
823 // WRITE_GAP = 128; (16*8)
824 // WRITE_1 = 256 32*8; (32*8)
825
826 // These timings work for 4469/4269/4305 (with the 55*8 above)
827 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
828
829 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
830
831 // Write one bit to card
832 void T55xxWriteBit(int bit)
833 {
834 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
835 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
836 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
837 if (!bit)
838 SpinDelayUs(WRITE_0);
839 else
840 SpinDelayUs(WRITE_1);
841 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
842 SpinDelayUs(WRITE_GAP);
843 }
844
845 // Write one card block in page 0, no lock
846 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
847 {
848 uint32_t i = 0;
849
850 // Set up FPGA, 125kHz
851 // Wait for config.. (192+8190xPOW)x8 == 67ms
852 LFSetupFPGAForADC(0, true);
853
854 // Now start writting
855 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
856 SpinDelayUs(START_GAP);
857
858 // Opcode
859 T55xxWriteBit(1);
860 T55xxWriteBit(0); //Page 0
861 if (PwdMode == 1){
862 // Pwd
863 for (i = 0x80000000; i != 0; i >>= 1)
864 T55xxWriteBit(Pwd & i);
865 }
866 // Lock bit
867 T55xxWriteBit(0);
868
869 // Data
870 for (i = 0x80000000; i != 0; i >>= 1)
871 T55xxWriteBit(Data & i);
872
873 // Block
874 for (i = 0x04; i != 0; i >>= 1)
875 T55xxWriteBit(Block & i);
876
877 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
878 // so wait a little more)
879 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
880 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
881 SpinDelay(20);
882 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
883 }
884
885 // Read one card block in page 0
886 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
887 {
888 uint8_t *dest = BigBuf_get_addr();
889 //uint16_t bufferlength = BigBuf_max_traceLen();
890 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
891 uint32_t i = 0;
892 // Clear destination buffer before sending the command 0x80 = average.
893 memset(dest, 0x80, bufferlength);
894
895 // Set up FPGA, 125kHz
896 // Wait for config.. (192+8190xPOW)x8 == 67ms
897 LFSetupFPGAForADC(0, true);
898 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
899 SpinDelayUs(START_GAP);
900
901 // Opcode
902 T55xxWriteBit(1);
903 T55xxWriteBit(0); //Page 0
904 if (PwdMode == 1){
905 // Pwd
906 for (i = 0x80000000; i != 0; i >>= 1)
907 T55xxWriteBit(Pwd & i);
908 }
909 // Lock bit
910 T55xxWriteBit(0);
911 // Block
912 for (i = 0x04; i != 0; i >>= 1)
913 T55xxWriteBit(Block & i);
914
915 // Turn field on to read the response
916 TurnReadLFOn();
917
918 // Now do the acquisition
919 i = 0;
920 for(;;) {
921 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
922 AT91C_BASE_SSC->SSC_THR = 0x43;
923 //AT91C_BASE_SSC->SSC_THR = 0xff;
924 LED_D_ON();
925 }
926 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
927 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
928 ++i;
929 LED_D_OFF();
930 if (i >= bufferlength) break;
931 }
932 }
933
934 cmd_send(CMD_ACK,0,0,0,0,0);
935 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
936 LED_D_OFF();
937 }
938
939 // Read card traceability data (page 1)
940 void T55xxReadTrace(void){
941 uint8_t *dest = BigBuf_get_addr();
942 //uint16_t bufferlength = BigBuf_max_traceLen();
943 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
944 uint32_t i = 0;
945
946 // Clear destination buffer before sending the command 0x80 = average
947 memset(dest, 0x80, bufferlength);
948
949 LFSetupFPGAForADC(0, true);
950 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
951 SpinDelayUs(START_GAP);
952
953 // Opcode
954 T55xxWriteBit(1);
955 T55xxWriteBit(1); //Page 1
956
957 // Turn field on to read the response
958 TurnReadLFOn();
959
960 // Now do the acquisition
961 for(;;) {
962 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
963 AT91C_BASE_SSC->SSC_THR = 0x43;
964 LED_D_ON();
965 }
966 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
967 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
968 ++i;
969 LED_D_OFF();
970
971 if (i >= bufferlength) break;
972 }
973 }
974
975 cmd_send(CMD_ACK,0,0,0,0,0);
976 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
977 LED_D_OFF();
978 }
979
980 void TurnReadLFOn(){
981 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
982 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
983 // Give it a bit of time for the resonant antenna to settle.
984 //SpinDelay(30);
985 SpinDelayUs(8*150);
986 }
987
988 /*-------------- Cloning routines -----------*/
989 // Copy HID id to card and setup block 0 config
990 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
991 {
992 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
993 int last_block = 0;
994
995 if (longFMT){
996 // Ensure no more than 84 bits supplied
997 if (hi2>0xFFFFF) {
998 DbpString("Tags can only have 84 bits.");
999 return;
1000 }
1001 // Build the 6 data blocks for supplied 84bit ID
1002 last_block = 6;
1003 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1004 for (int i=0;i<4;i++) {
1005 if (hi2 & (1<<(19-i)))
1006 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1007 else
1008 data1 |= (1<<((3-i)*2)); // 0 -> 01
1009 }
1010
1011 data2 = 0;
1012 for (int i=0;i<16;i++) {
1013 if (hi2 & (1<<(15-i)))
1014 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1015 else
1016 data2 |= (1<<((15-i)*2)); // 0 -> 01
1017 }
1018
1019 data3 = 0;
1020 for (int i=0;i<16;i++) {
1021 if (hi & (1<<(31-i)))
1022 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1023 else
1024 data3 |= (1<<((15-i)*2)); // 0 -> 01
1025 }
1026
1027 data4 = 0;
1028 for (int i=0;i<16;i++) {
1029 if (hi & (1<<(15-i)))
1030 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1031 else
1032 data4 |= (1<<((15-i)*2)); // 0 -> 01
1033 }
1034
1035 data5 = 0;
1036 for (int i=0;i<16;i++) {
1037 if (lo & (1<<(31-i)))
1038 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1039 else
1040 data5 |= (1<<((15-i)*2)); // 0 -> 01
1041 }
1042
1043 data6 = 0;
1044 for (int i=0;i<16;i++) {
1045 if (lo & (1<<(15-i)))
1046 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1047 else
1048 data6 |= (1<<((15-i)*2)); // 0 -> 01
1049 }
1050 }
1051 else {
1052 // Ensure no more than 44 bits supplied
1053 if (hi>0xFFF) {
1054 DbpString("Tags can only have 44 bits.");
1055 return;
1056 }
1057
1058 // Build the 3 data blocks for supplied 44bit ID
1059 last_block = 3;
1060
1061 data1 = 0x1D000000; // load preamble
1062
1063 for (int i=0;i<12;i++) {
1064 if (hi & (1<<(11-i)))
1065 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1066 else
1067 data1 |= (1<<((11-i)*2)); // 0 -> 01
1068 }
1069
1070 data2 = 0;
1071 for (int i=0;i<16;i++) {
1072 if (lo & (1<<(31-i)))
1073 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1074 else
1075 data2 |= (1<<((15-i)*2)); // 0 -> 01
1076 }
1077
1078 data3 = 0;
1079 for (int i=0;i<16;i++) {
1080 if (lo & (1<<(15-i)))
1081 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1082 else
1083 data3 |= (1<<((15-i)*2)); // 0 -> 01
1084 }
1085 }
1086
1087 LED_D_ON();
1088 // Program the data blocks for supplied ID
1089 // and the block 0 for HID format
1090 T55xxWriteBlock(data1,1,0,0);
1091 T55xxWriteBlock(data2,2,0,0);
1092 T55xxWriteBlock(data3,3,0,0);
1093
1094 if (longFMT) { // if long format there are 6 blocks
1095 T55xxWriteBlock(data4,4,0,0);
1096 T55xxWriteBlock(data5,5,0,0);
1097 T55xxWriteBlock(data6,6,0,0);
1098 }
1099
1100 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1101 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1102 T55x7_MODULATION_FSK2a |
1103 last_block << T55x7_MAXBLOCK_SHIFT,
1104 0,0,0);
1105
1106 LED_D_OFF();
1107
1108 DbpString("DONE!");
1109 }
1110
1111 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1112 {
1113 int data1=0, data2=0; //up to six blocks for long format
1114
1115 data1 = hi; // load preamble
1116 data2 = lo;
1117
1118 LED_D_ON();
1119 // Program the data blocks for supplied ID
1120 // and the block 0 for HID format
1121 T55xxWriteBlock(data1,1,0,0);
1122 T55xxWriteBlock(data2,2,0,0);
1123
1124 //Config Block
1125 T55xxWriteBlock(0x00147040,0,0,0);
1126 LED_D_OFF();
1127
1128 DbpString("DONE!");
1129 }
1130
1131 // Define 9bit header for EM410x tags
1132 #define EM410X_HEADER 0x1FF
1133 #define EM410X_ID_LENGTH 40
1134
1135 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1136 {
1137 int i, id_bit;
1138 uint64_t id = EM410X_HEADER;
1139 uint64_t rev_id = 0; // reversed ID
1140 int c_parity[4]; // column parity
1141 int r_parity = 0; // row parity
1142 uint32_t clock = 0;
1143
1144 // Reverse ID bits given as parameter (for simpler operations)
1145 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1146 if (i < 32) {
1147 rev_id = (rev_id << 1) | (id_lo & 1);
1148 id_lo >>= 1;
1149 } else {
1150 rev_id = (rev_id << 1) | (id_hi & 1);
1151 id_hi >>= 1;
1152 }
1153 }
1154
1155 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1156 id_bit = rev_id & 1;
1157
1158 if (i % 4 == 0) {
1159 // Don't write row parity bit at start of parsing
1160 if (i)
1161 id = (id << 1) | r_parity;
1162 // Start counting parity for new row
1163 r_parity = id_bit;
1164 } else {
1165 // Count row parity
1166 r_parity ^= id_bit;
1167 }
1168
1169 // First elements in column?
1170 if (i < 4)
1171 // Fill out first elements
1172 c_parity[i] = id_bit;
1173 else
1174 // Count column parity
1175 c_parity[i % 4] ^= id_bit;
1176
1177 // Insert ID bit
1178 id = (id << 1) | id_bit;
1179 rev_id >>= 1;
1180 }
1181
1182 // Insert parity bit of last row
1183 id = (id << 1) | r_parity;
1184
1185 // Fill out column parity at the end of tag
1186 for (i = 0; i < 4; ++i)
1187 id = (id << 1) | c_parity[i];
1188
1189 // Add stop bit
1190 id <<= 1;
1191
1192 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1193 LED_D_ON();
1194
1195 // Write EM410x ID
1196 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1197 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1198
1199 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1200 if (card) {
1201 // Clock rate is stored in bits 8-15 of the card value
1202 clock = (card & 0xFF00) >> 8;
1203 Dbprintf("Clock rate: %d", clock);
1204 switch (clock)
1205 {
1206 case 32:
1207 clock = T55x7_BITRATE_RF_32;
1208 break;
1209 case 16:
1210 clock = T55x7_BITRATE_RF_16;
1211 break;
1212 case 0:
1213 // A value of 0 is assumed to be 64 for backwards-compatibility
1214 // Fall through...
1215 case 64:
1216 clock = T55x7_BITRATE_RF_64;
1217 break;
1218 default:
1219 Dbprintf("Invalid clock rate: %d", clock);
1220 return;
1221 }
1222
1223 // Writing configuration for T55x7 tag
1224 T55xxWriteBlock(clock |
1225 T55x7_MODULATION_MANCHESTER |
1226 2 << T55x7_MAXBLOCK_SHIFT,
1227 0, 0, 0);
1228 }
1229 else
1230 // Writing configuration for T5555(Q5) tag
1231 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1232 T5555_MODULATION_MANCHESTER |
1233 2 << T5555_MAXBLOCK_SHIFT,
1234 0, 0, 0);
1235
1236 LED_D_OFF();
1237 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1238 (uint32_t)(id >> 32), (uint32_t)id);
1239 }
1240
1241 // Clone Indala 64-bit tag by UID to T55x7
1242 void CopyIndala64toT55x7(int hi, int lo)
1243 {
1244
1245 //Program the 2 data blocks for supplied 64bit UID
1246 // and the block 0 for Indala64 format
1247 T55xxWriteBlock(hi,1,0,0);
1248 T55xxWriteBlock(lo,2,0,0);
1249 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1250 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1251 T55x7_MODULATION_PSK1 |
1252 2 << T55x7_MAXBLOCK_SHIFT,
1253 0, 0, 0);
1254 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1255 // T5567WriteBlock(0x603E1042,0);
1256
1257 DbpString("DONE!");
1258
1259 }
1260
1261 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1262 {
1263
1264 //Program the 7 data blocks for supplied 224bit UID
1265 // and the block 0 for Indala224 format
1266 T55xxWriteBlock(uid1,1,0,0);
1267 T55xxWriteBlock(uid2,2,0,0);
1268 T55xxWriteBlock(uid3,3,0,0);
1269 T55xxWriteBlock(uid4,4,0,0);
1270 T55xxWriteBlock(uid5,5,0,0);
1271 T55xxWriteBlock(uid6,6,0,0);
1272 T55xxWriteBlock(uid7,7,0,0);
1273 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1274 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1275 T55x7_MODULATION_PSK1 |
1276 7 << T55x7_MAXBLOCK_SHIFT,
1277 0,0,0);
1278 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1279 // T5567WriteBlock(0x603E10E2,0);
1280
1281 DbpString("DONE!");
1282
1283 }
1284
1285
1286 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1287 #define max(x,y) ( x<y ? y:x)
1288
1289 int DemodPCF7931(uint8_t **outBlocks) {
1290 uint8_t BitStream[256];
1291 uint8_t Blocks[8][16];
1292 uint8_t *GraphBuffer = BigBuf_get_addr();
1293 int GraphTraceLen = BigBuf_max_traceLen();
1294 int i, j, lastval, bitidx, half_switch;
1295 int clock = 64;
1296 int tolerance = clock / 8;
1297 int pmc, block_done;
1298 int lc, warnings = 0;
1299 int num_blocks = 0;
1300 int lmin=128, lmax=128;
1301 uint8_t dir;
1302
1303 LFSetupFPGAForADC(95, true);
1304 DoAcquisition_default(0, 0);
1305
1306
1307 lmin = 64;
1308 lmax = 192;
1309
1310 i = 2;
1311
1312 /* Find first local max/min */
1313 if(GraphBuffer[1] > GraphBuffer[0]) {
1314 while(i < GraphTraceLen) {
1315 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1316 break;
1317 i++;
1318 }
1319 dir = 0;
1320 }
1321 else {
1322 while(i < GraphTraceLen) {
1323 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1324 break;
1325 i++;
1326 }
1327 dir = 1;
1328 }
1329
1330 lastval = i++;
1331 half_switch = 0;
1332 pmc = 0;
1333 block_done = 0;
1334
1335 for (bitidx = 0; i < GraphTraceLen; i++)
1336 {
1337 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1338 {
1339 lc = i - lastval;
1340 lastval = i;
1341
1342 // Switch depending on lc length:
1343 // Tolerance is 1/8 of clock rate (arbitrary)
1344 if (abs(lc-clock/4) < tolerance) {
1345 // 16T0
1346 if((i - pmc) == lc) { /* 16T0 was previous one */
1347 /* It's a PMC ! */
1348 i += (128+127+16+32+33+16)-1;
1349 lastval = i;
1350 pmc = 0;
1351 block_done = 1;
1352 }
1353 else {
1354 pmc = i;
1355 }
1356 } else if (abs(lc-clock/2) < tolerance) {
1357 // 32TO
1358 if((i - pmc) == lc) { /* 16T0 was previous one */
1359 /* It's a PMC ! */
1360 i += (128+127+16+32+33)-1;
1361 lastval = i;
1362 pmc = 0;
1363 block_done = 1;
1364 }
1365 else if(half_switch == 1) {
1366 BitStream[bitidx++] = 0;
1367 half_switch = 0;
1368 }
1369 else
1370 half_switch++;
1371 } else if (abs(lc-clock) < tolerance) {
1372 // 64TO
1373 BitStream[bitidx++] = 1;
1374 } else {
1375 // Error
1376 warnings++;
1377 if (warnings > 10)
1378 {
1379 Dbprintf("Error: too many detection errors, aborting.");
1380 return 0;
1381 }
1382 }
1383
1384 if(block_done == 1) {
1385 if(bitidx == 128) {
1386 for(j=0; j<16; j++) {
1387 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1388 64*BitStream[j*8+6]+
1389 32*BitStream[j*8+5]+
1390 16*BitStream[j*8+4]+
1391 8*BitStream[j*8+3]+
1392 4*BitStream[j*8+2]+
1393 2*BitStream[j*8+1]+
1394 BitStream[j*8];
1395 }
1396 num_blocks++;
1397 }
1398 bitidx = 0;
1399 block_done = 0;
1400 half_switch = 0;
1401 }
1402 if(i < GraphTraceLen)
1403 {
1404 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1405 else dir = 1;
1406 }
1407 }
1408 if(bitidx==255)
1409 bitidx=0;
1410 warnings = 0;
1411 if(num_blocks == 4) break;
1412 }
1413 memcpy(outBlocks, Blocks, 16*num_blocks);
1414 return num_blocks;
1415 }
1416
1417 int IsBlock0PCF7931(uint8_t *Block) {
1418 // Assume RFU means 0 :)
1419 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1420 return 1;
1421 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1422 return 1;
1423 return 0;
1424 }
1425
1426 int IsBlock1PCF7931(uint8_t *Block) {
1427 // Assume RFU means 0 :)
1428 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1429 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1430 return 1;
1431
1432 return 0;
1433 }
1434
1435 #define ALLOC 16
1436
1437 void ReadPCF7931() {
1438 uint8_t Blocks[8][17];
1439 uint8_t tmpBlocks[4][16];
1440 int i, j, ind, ind2, n;
1441 int num_blocks = 0;
1442 int max_blocks = 8;
1443 int ident = 0;
1444 int error = 0;
1445 int tries = 0;
1446
1447 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1448
1449 do {
1450 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1451 n = DemodPCF7931((uint8_t**)tmpBlocks);
1452 if(!n)
1453 error++;
1454 if(error==10 && num_blocks == 0) {
1455 Dbprintf("Error, no tag or bad tag");
1456 return;
1457 }
1458 else if (tries==20 || error==10) {
1459 Dbprintf("Error reading the tag");
1460 Dbprintf("Here is the partial content");
1461 goto end;
1462 }
1463
1464 for(i=0; i<n; i++)
1465 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1466 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1467 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1468 if(!ident) {
1469 for(i=0; i<n; i++) {
1470 if(IsBlock0PCF7931(tmpBlocks[i])) {
1471 // Found block 0 ?
1472 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1473 // Found block 1!
1474 // \o/
1475 ident = 1;
1476 memcpy(Blocks[0], tmpBlocks[i], 16);
1477 Blocks[0][ALLOC] = 1;
1478 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1479 Blocks[1][ALLOC] = 1;
1480 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1481 // Debug print
1482 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1483 num_blocks = 2;
1484 // Handle following blocks
1485 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1486 if(j==n) j=0;
1487 if(j==i) break;
1488 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1489 Blocks[ind2][ALLOC] = 1;
1490 }
1491 break;
1492 }
1493 }
1494 }
1495 }
1496 else {
1497 for(i=0; i<n; i++) { // Look for identical block in known blocks
1498 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1499 for(j=0; j<max_blocks; j++) {
1500 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1501 // Found an identical block
1502 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1503 if(ind2 < 0)
1504 ind2 = max_blocks;
1505 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1506 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1507 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1508 Blocks[ind2][ALLOC] = 1;
1509 num_blocks++;
1510 if(num_blocks == max_blocks) goto end;
1511 }
1512 }
1513 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1514 if(ind2 > max_blocks)
1515 ind2 = 0;
1516 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1517 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1518 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1519 Blocks[ind2][ALLOC] = 1;
1520 num_blocks++;
1521 if(num_blocks == max_blocks) goto end;
1522 }
1523 }
1524 }
1525 }
1526 }
1527 }
1528 }
1529 tries++;
1530 if (BUTTON_PRESS()) return;
1531 } while (num_blocks != max_blocks);
1532 end:
1533 Dbprintf("-----------------------------------------");
1534 Dbprintf("Memory content:");
1535 Dbprintf("-----------------------------------------");
1536 for(i=0; i<max_blocks; i++) {
1537 if(Blocks[i][ALLOC]==1)
1538 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1539 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1540 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1541 else
1542 Dbprintf("<missing block %d>", i);
1543 }
1544 Dbprintf("-----------------------------------------");
1545
1546 return ;
1547 }
1548
1549
1550 //-----------------------------------
1551 // EM4469 / EM4305 routines
1552 //-----------------------------------
1553 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1554 #define FWD_CMD_WRITE 0xA
1555 #define FWD_CMD_READ 0x9
1556 #define FWD_CMD_DISABLE 0x5
1557
1558
1559 uint8_t forwardLink_data[64]; //array of forwarded bits
1560 uint8_t * forward_ptr; //ptr for forward message preparation
1561 uint8_t fwd_bit_sz; //forwardlink bit counter
1562 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1563
1564 //====================================================================
1565 // prepares command bits
1566 // see EM4469 spec
1567 //====================================================================
1568 //--------------------------------------------------------------------
1569 uint8_t Prepare_Cmd( uint8_t cmd ) {
1570 //--------------------------------------------------------------------
1571
1572 *forward_ptr++ = 0; //start bit
1573 *forward_ptr++ = 0; //second pause for 4050 code
1574
1575 *forward_ptr++ = cmd;
1576 cmd >>= 1;
1577 *forward_ptr++ = cmd;
1578 cmd >>= 1;
1579 *forward_ptr++ = cmd;
1580 cmd >>= 1;
1581 *forward_ptr++ = cmd;
1582
1583 return 6; //return number of emited bits
1584 }
1585
1586 //====================================================================
1587 // prepares address bits
1588 // see EM4469 spec
1589 //====================================================================
1590
1591 //--------------------------------------------------------------------
1592 uint8_t Prepare_Addr( uint8_t addr ) {
1593 //--------------------------------------------------------------------
1594
1595 register uint8_t line_parity;
1596
1597 uint8_t i;
1598 line_parity = 0;
1599 for(i=0;i<6;i++) {
1600 *forward_ptr++ = addr;
1601 line_parity ^= addr;
1602 addr >>= 1;
1603 }
1604
1605 *forward_ptr++ = (line_parity & 1);
1606
1607 return 7; //return number of emited bits
1608 }
1609
1610 //====================================================================
1611 // prepares data bits intreleaved with parity bits
1612 // see EM4469 spec
1613 //====================================================================
1614
1615 //--------------------------------------------------------------------
1616 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1617 //--------------------------------------------------------------------
1618
1619 register uint8_t line_parity;
1620 register uint8_t column_parity;
1621 register uint8_t i, j;
1622 register uint16_t data;
1623
1624 data = data_low;
1625 column_parity = 0;
1626
1627 for(i=0; i<4; i++) {
1628 line_parity = 0;
1629 for(j=0; j<8; j++) {
1630 line_parity ^= data;
1631 column_parity ^= (data & 1) << j;
1632 *forward_ptr++ = data;
1633 data >>= 1;
1634 }
1635 *forward_ptr++ = line_parity;
1636 if(i == 1)
1637 data = data_hi;
1638 }
1639
1640 for(j=0; j<8; j++) {
1641 *forward_ptr++ = column_parity;
1642 column_parity >>= 1;
1643 }
1644 *forward_ptr = 0;
1645
1646 return 45; //return number of emited bits
1647 }
1648
1649 //====================================================================
1650 // Forward Link send function
1651 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1652 // fwd_bit_count set with number of bits to be sent
1653 //====================================================================
1654 void SendForward(uint8_t fwd_bit_count) {
1655
1656 fwd_write_ptr = forwardLink_data;
1657 fwd_bit_sz = fwd_bit_count;
1658
1659 LED_D_ON();
1660
1661 //Field on
1662 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1663 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1664 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1665
1666 // Give it a bit of time for the resonant antenna to settle.
1667 // And for the tag to fully power up
1668 SpinDelay(150);
1669
1670 // force 1st mod pulse (start gap must be longer for 4305)
1671 fwd_bit_sz--; //prepare next bit modulation
1672 fwd_write_ptr++;
1673 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1674 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1675 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1676 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1677 SpinDelayUs(16*8); //16 cycles on (8us each)
1678
1679 // now start writting
1680 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1681 if(((*fwd_write_ptr++) & 1) == 1)
1682 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1683 else {
1684 //These timings work for 4469/4269/4305 (with the 55*8 above)
1685 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1686 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1687 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1688 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1689 SpinDelayUs(9*8); //16 cycles on (8us each)
1690 }
1691 }
1692 }
1693
1694 void EM4xLogin(uint32_t Password) {
1695
1696 uint8_t fwd_bit_count;
1697
1698 forward_ptr = forwardLink_data;
1699 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1700 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1701
1702 SendForward(fwd_bit_count);
1703
1704 //Wait for command to complete
1705 SpinDelay(20);
1706
1707 }
1708
1709 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1710
1711 uint8_t *dest = BigBuf_get_addr();
1712 uint16_t bufferlength = BigBuf_max_traceLen();
1713 uint32_t i = 0;
1714
1715 // Clear destination buffer before sending the command 0x80 = average.
1716 memset(dest, 0x80, bufferlength);
1717
1718 uint8_t fwd_bit_count;
1719
1720 //If password mode do login
1721 if (PwdMode == 1) EM4xLogin(Pwd);
1722
1723 forward_ptr = forwardLink_data;
1724 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1725 fwd_bit_count += Prepare_Addr( Address );
1726
1727 // Connect the A/D to the peak-detected low-frequency path.
1728 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1729 // Now set up the SSC to get the ADC samples that are now streaming at us.
1730 FpgaSetupSsc();
1731
1732 SendForward(fwd_bit_count);
1733
1734 // Now do the acquisition
1735 i = 0;
1736 for(;;) {
1737 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1738 AT91C_BASE_SSC->SSC_THR = 0x43;
1739 }
1740 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1741 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1742 ++i;
1743 if (i >= bufferlength) break;
1744 }
1745 }
1746
1747 cmd_send(CMD_ACK,0,0,0,0,0);
1748 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1749 LED_D_OFF();
1750 }
1751
1752 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1753
1754 uint8_t fwd_bit_count;
1755
1756 //If password mode do login
1757 if (PwdMode == 1) EM4xLogin(Pwd);
1758
1759 forward_ptr = forwardLink_data;
1760 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1761 fwd_bit_count += Prepare_Addr( Address );
1762 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1763
1764 SendForward(fwd_bit_count);
1765
1766 //Wait for write to complete
1767 SpinDelay(20);
1768 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1769 LED_D_OFF();
1770 }
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