]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ADD: added the possibility to load a default pwd file to be used with the "lf t55xx...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" //test
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
206 if (crc != (shift2&0xffff)) {
207 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
208 } else {
209 DbpString("Info: CRC is good");
210 }
211 }
212 }
213
214 void WriteTIbyte(uint8_t b)
215 {
216 int i = 0;
217
218 // modulate 8 bits out to the antenna
219 for (i=0; i<8; i++)
220 {
221 if (b&(1<<i)) {
222 // stop modulating antenna
223 LOW(GPIO_SSC_DOUT);
224 SpinDelayUs(1000);
225 // modulate antenna
226 HIGH(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 } else {
229 // stop modulating antenna
230 LOW(GPIO_SSC_DOUT);
231 SpinDelayUs(300);
232 // modulate antenna
233 HIGH(GPIO_SSC_DOUT);
234 SpinDelayUs(1700);
235 }
236 }
237 }
238
239 void AcquireTiType(void)
240 {
241 int i, j, n;
242 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
243 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
244 #define TIBUFLEN 1250
245
246 // clear buffer
247 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
248
249 //clear buffer now so it does not interfere with timing later
250 BigBuf_Clear_ext(false);
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN * 32;
300
301 // unpack buffer
302 for (i = TIBUFLEN-1; i >= 0; i--) {
303 for (j = 0; j < 32; j++) {
304 if(buf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311 }
312
313 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314 // if crc provided, it will be written with the data verbatim (even if bogus)
315 // if not provided a valid crc will be computed from the data and written.
316 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317 {
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb first
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use 'lf ti read' to check");
382 }
383
384 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385 {
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol) LED_D_ON();
410
411 if(tab[i])
412 OPEN_COIL();
413 else
414 SHORT_COIL();
415
416 if (ledcontrol) LED_D_OFF();
417
418 //wait until SSC_CLK goes LOW
419 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
420 if(BUTTON_PRESS()) {
421 DbpString("Stopped");
422 return;
423 }
424 WDT_HIT();
425 }
426
427 i++;
428 if(i == period) {
429
430 i = 0;
431 if (gap) {
432 SHORT_COIL();
433 SpinDelayUs(gap);
434 }
435 }
436 }
437 }
438
439 #define DEBUG_FRAME_CONTENTS 1
440 void SimulateTagLowFrequencyBidir(int divisor, int t0)
441 {
442 }
443
444 // compose fc/8 fc/10 waveform (FSK2)
445 static void fc(int c, int *n)
446 {
447 uint8_t *dest = BigBuf_get_addr();
448 int idx;
449
450 // for when we want an fc8 pattern every 4 logical bits
451 if(c==0) {
452 dest[((*n)++)]=1;
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 }
461
462 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
463 if(c==8) {
464 for (idx=0; idx<6; idx++) {
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 }
474 }
475
476 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
477 if(c==10) {
478 for (idx=0; idx<5; idx++) {
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490 }
491 }
492 // compose fc/X fc/Y waveform (FSKx)
493 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
494 {
495 uint8_t *dest = BigBuf_get_addr();
496 uint8_t halfFC = fc/2;
497 uint8_t wavesPerClock = clock/fc;
498 uint8_t mod = clock % fc; //modifier
499 uint8_t modAdj = fc/mod; //how often to apply modifier
500 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
501 // loop through clock - step field clock
502 for (uint8_t idx=0; idx < wavesPerClock; idx++){
503 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
504 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
505 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
506 *n += fc;
507 }
508 if (mod>0) (*modCnt)++;
509 if ((mod>0) && modAdjOk){ //fsk2
510 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
511 memset(dest+(*n), 0, fc-halfFC);
512 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
513 *n += fc;
514 }
515 }
516 if (mod>0 && !modAdjOk){ //fsk1
517 memset(dest+(*n), 0, mod-(mod/2));
518 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
519 *n += mod;
520 }
521 }
522
523 // prepare a waveform pattern in the buffer based on the ID given then
524 // simulate a HID tag until the button is pressed
525 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
526 {
527 int n=0, i=0;
528 /*
529 HID tag bitstream format
530 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
531 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
532 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
533 A fc8 is inserted before every 4 bits
534 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
535 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
536 */
537
538 if (hi>0xFFF) {
539 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
540 return;
541 }
542 fc(0,&n);
543 // special start of frame marker containing invalid bit sequences
544 fc(8, &n); fc(8, &n); // invalid
545 fc(8, &n); fc(10, &n); // logical 0
546 fc(10, &n); fc(10, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548
549 WDT_HIT();
550 // manchester encode bits 43 to 32
551 for (i=11; i>=0; i--) {
552 if ((i%4)==3) fc(0,&n);
553 if ((hi>>i)&1) {
554 fc(10, &n); fc(8, &n); // low-high transition
555 } else {
556 fc(8, &n); fc(10, &n); // high-low transition
557 }
558 }
559
560 WDT_HIT();
561 // manchester encode bits 31 to 0
562 for (i=31; i>=0; i--) {
563 if ((i%4)==3) fc(0,&n);
564 if ((lo>>i)&1) {
565 fc(10, &n); fc(8, &n); // low-high transition
566 } else {
567 fc(8, &n); fc(10, &n); // high-low transition
568 }
569 }
570
571 if (ledcontrol) LED_A_ON();
572 SimulateTagLowFrequency(n, 0, ledcontrol);
573 if (ledcontrol) LED_A_OFF();
574 }
575
576 // prepare a waveform pattern in the buffer based on the ID given then
577 // simulate a FSK tag until the button is pressed
578 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
579 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
580 {
581 int ledcontrol=1;
582 int n=0, i=0;
583 uint8_t fcHigh = arg1 >> 8;
584 uint8_t fcLow = arg1 & 0xFF;
585 uint16_t modCnt = 0;
586 uint8_t clk = arg2 & 0xFF;
587 uint8_t invert = (arg2 >> 8) & 1;
588
589 for (i=0; i<size; i++){
590 if (BitStream[i] == invert){
591 fcAll(fcLow, &n, clk, &modCnt);
592 } else {
593 fcAll(fcHigh, &n, clk, &modCnt);
594 }
595 }
596 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
597 /*Dbprintf("DEBUG: First 32:");
598 uint8_t *dest = BigBuf_get_addr();
599 i=0;
600 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
601 i+=16;
602 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
603 */
604 if (ledcontrol)
605 LED_A_ON();
606
607 SimulateTagLowFrequency(n, 0, ledcontrol);
608
609 if (ledcontrol)
610 LED_A_OFF();
611 }
612
613 // compose ask waveform for one bit(ASK)
614 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
615 {
616 uint8_t *dest = BigBuf_get_addr();
617 uint8_t halfClk = clock/2;
618 // c = current bit 1 or 0
619 if (manchester==1){
620 memset(dest+(*n), c, halfClk);
621 memset(dest+(*n) + halfClk, c^1, halfClk);
622 } else {
623 memset(dest+(*n), c, clock);
624 }
625 *n += clock;
626 }
627
628 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
629 {
630 uint8_t *dest = BigBuf_get_addr();
631 uint8_t halfClk = clock/2;
632 if (c){
633 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
634 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
635 } else {
636 memset(dest+(*n), c ^ *phase, clock);
637 *phase ^= 1;
638 }
639
640 }
641
642 // args clock, ask/man or askraw, invert, transmission separator
643 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
644 {
645 int ledcontrol = 1;
646 int n=0, i=0;
647 uint8_t clk = (arg1 >> 8) & 0xFF;
648 uint8_t encoding = arg1 & 0xFF;
649 uint8_t separator = arg2 & 1;
650 uint8_t invert = (arg2 >> 8) & 1;
651
652 if (encoding==2){ //biphase
653 uint8_t phase=0;
654 for (i=0; i<size; i++){
655 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
656 }
657 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
658 for (i=0; i<size; i++){
659 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
660 }
661 }
662 } else { // ask/manchester || ask/raw
663 for (i=0; i<size; i++){
664 askSimBit(BitStream[i]^invert, &n, clk, encoding);
665 }
666 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
667 for (i=0; i<size; i++){
668 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
669 }
670 }
671 }
672
673 if (separator==1) Dbprintf("sorry but separator option not yet available");
674
675 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
676
677 if (ledcontrol) LED_A_ON();
678 SimulateTagLowFrequency(n, 0, ledcontrol);
679 if (ledcontrol) LED_A_OFF();
680 }
681
682 //carrier can be 2,4 or 8
683 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
684 {
685 uint8_t *dest = BigBuf_get_addr();
686 uint8_t halfWave = waveLen/2;
687 //uint8_t idx;
688 int i = 0;
689 if (phaseChg){
690 // write phase change
691 memset(dest+(*n), *curPhase^1, halfWave);
692 memset(dest+(*n) + halfWave, *curPhase, halfWave);
693 *n += waveLen;
694 *curPhase ^= 1;
695 i += waveLen;
696 }
697 //write each normal clock wave for the clock duration
698 for (; i < clk; i+=waveLen){
699 memset(dest+(*n), *curPhase, halfWave);
700 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
701 *n += waveLen;
702 }
703 }
704
705 // args clock, carrier, invert,
706 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
707 {
708 int ledcontrol = 1;
709 int n=0, i=0;
710 uint8_t clk = arg1 >> 8;
711 uint8_t carrier = arg1 & 0xFF;
712 uint8_t invert = arg2 & 0xFF;
713 uint8_t curPhase = 0;
714 for (i=0; i<size; i++){
715 if (BitStream[i] == curPhase){
716 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
717 } else {
718 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
719 }
720 }
721 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
722
723 if (ledcontrol) LED_A_ON();
724 SimulateTagLowFrequency(n, 0, ledcontrol);
725 if (ledcontrol) LED_A_OFF();
726 }
727
728 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
729 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
730 {
731 uint8_t *dest = BigBuf_get_addr();
732 size_t size = 0;
733 uint32_t hi2=0, hi=0, lo=0;
734 int idx=0;
735 // Configure to go in 125Khz listen mode
736 LFSetupFPGAForADC(95, true);
737
738 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
739
740 WDT_HIT();
741 if (ledcontrol) LED_A_ON();
742
743 DoAcquisition_default(-1,true);
744 // FSK demodulator
745 size = 50*128*2; //big enough to catch 2 sequences of largest format
746 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
747
748 if (idx>0 && lo>0 && (size==96 || size==192)){
749 // go over previously decoded manchester data and decode into usable tag ID
750 if (hi2 != 0){ //extra large HID tags 88/192 bits
751 Dbprintf("TAG ID: %x%08x%08x (%d)",
752 (unsigned int) hi2,
753 (unsigned int) hi,
754 (unsigned int) lo,
755 (unsigned int) (lo>>1) & 0xFFFF
756 );
757 }else { //standard HID tags 44/96 bits
758 uint8_t bitlen = 0;
759 uint32_t fc = 0;
760 uint32_t cardnum = 0;
761
762 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
763 uint32_t lo2=0;
764 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
765 uint8_t idx3 = 1;
766 while(lo2 > 1){ //find last bit set to 1 (format len bit)
767 lo2=lo2 >> 1;
768 idx3++;
769 }
770 bitlen = idx3+19;
771 fc =0;
772 cardnum=0;
773 if(bitlen == 26){
774 cardnum = (lo>>1)&0xFFFF;
775 fc = (lo>>17)&0xFF;
776 }
777 if(bitlen == 37){
778 cardnum = (lo>>1)&0x7FFFF;
779 fc = ((hi&0xF)<<12)|(lo>>20);
780 }
781 if(bitlen == 34){
782 cardnum = (lo>>1)&0xFFFF;
783 fc= ((hi&1)<<15)|(lo>>17);
784 }
785 if(bitlen == 35){
786 cardnum = (lo>>1)&0xFFFFF;
787 fc = ((hi&1)<<11)|(lo>>21);
788 }
789 }
790 else { //if bit 38 is not set then 37 bit format is used
791 bitlen= 37;
792 fc =0;
793 cardnum=0;
794 if(bitlen==37){
795 cardnum = (lo>>1)&0x7FFFF;
796 fc = ((hi&0xF)<<12)|(lo>>20);
797 }
798 }
799 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
800 (unsigned int) hi,
801 (unsigned int) lo,
802 (unsigned int) (lo>>1) & 0xFFFF,
803 (unsigned int) bitlen,
804 (unsigned int) fc,
805 (unsigned int) cardnum);
806 }
807 if (findone){
808 if (ledcontrol) LED_A_OFF();
809 *high = hi;
810 *low = lo;
811 return;
812 }
813 // reset
814 }
815 hi2 = hi = lo = idx = 0;
816 WDT_HIT();
817 }
818 DbpString("Stopped");
819 if (ledcontrol) LED_A_OFF();
820 }
821
822 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
823 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
824 {
825 uint8_t *dest = BigBuf_get_addr();
826 size_t size;
827 int idx=0;
828 // Configure to go in 125Khz listen mode
829 LFSetupFPGAForADC(95, true);
830
831 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
832
833 WDT_HIT();
834 if (ledcontrol) LED_A_ON();
835
836 DoAcquisition_default(-1,true);
837 // FSK demodulator
838 size = 50*128*2; //big enough to catch 2 sequences of largest format
839 idx = AWIDdemodFSK(dest, &size);
840
841 if (idx<=0 || size!=96) continue;
842 // Index map
843 // 0 10 20 30 40 50 60
844 // | | | | | | |
845 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
846 // -----------------------------------------------------------------------------
847 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
848 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
849 // |---26 bit---| |-----117----||-------------142-------------|
850 // b = format bit len, o = odd parity of last 3 bits
851 // f = facility code, c = card number
852 // w = wiegand parity
853 // (26 bit format shown)
854
855 //get raw ID before removing parities
856 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
857 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
858 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
859
860 size = removeParity(dest, idx+8, 4, 1, 88);
861 if (size != 66) continue;
862 // ok valid card found!
863
864 // Index map
865 // 0 10 20 30 40 50 60
866 // | | | | | | |
867 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
868 // -----------------------------------------------------------------------------
869 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
870 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
871 // |26 bit| |-117--| |-----142------|
872 // b = format bit len, o = odd parity of last 3 bits
873 // f = facility code, c = card number
874 // w = wiegand parity
875 // (26 bit format shown)
876
877 uint32_t fc = 0;
878 uint32_t cardnum = 0;
879 uint32_t code1 = 0;
880 uint32_t code2 = 0;
881 uint8_t fmtLen = bytebits_to_byte(dest,8);
882 if (fmtLen==26){
883 fc = bytebits_to_byte(dest+9, 8);
884 cardnum = bytebits_to_byte(dest+17, 16);
885 code1 = bytebits_to_byte(dest+8,fmtLen);
886 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
887 } else {
888 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
889 if (fmtLen>32){
890 code1 = bytebits_to_byte(dest+8,fmtLen-32);
891 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
892 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
893 } else{
894 code1 = bytebits_to_byte(dest+8,fmtLen);
895 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
896 }
897 }
898 if (findone){
899 if (ledcontrol) LED_A_OFF();
900 return;
901 }
902 // reset
903 idx = 0;
904 WDT_HIT();
905 }
906 DbpString("Stopped");
907 if (ledcontrol) LED_A_OFF();
908 }
909
910 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
911 {
912 uint8_t *dest = BigBuf_get_addr();
913
914 size_t size=0, idx=0;
915 int clk=0, invert=0, errCnt=0, maxErr=20;
916 uint32_t hi=0;
917 uint64_t lo=0;
918 // Configure to go in 125Khz listen mode
919 LFSetupFPGAForADC(95, true);
920
921 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
922
923 WDT_HIT();
924 if (ledcontrol) LED_A_ON();
925
926 DoAcquisition_default(-1,true);
927 size = BigBuf_max_traceLen();
928 //askdemod and manchester decode
929 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
930 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
931 WDT_HIT();
932
933 if (errCnt<0) continue;
934
935 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
936 if (errCnt){
937 if (size>64){
938 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
939 hi,
940 (uint32_t)(lo>>32),
941 (uint32_t)lo,
942 (uint32_t)(lo&0xFFFF),
943 (uint32_t)((lo>>16LL) & 0xFF),
944 (uint32_t)(lo & 0xFFFFFF));
945 } else {
946 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
947 (uint32_t)(lo>>32),
948 (uint32_t)lo,
949 (uint32_t)(lo&0xFFFF),
950 (uint32_t)((lo>>16LL) & 0xFF),
951 (uint32_t)(lo & 0xFFFFFF));
952 }
953
954 if (findone){
955 if (ledcontrol) LED_A_OFF();
956 *high=lo>>32;
957 *low=lo & 0xFFFFFFFF;
958 return;
959 }
960 }
961 WDT_HIT();
962 hi = lo = size = idx = 0;
963 clk = invert = errCnt = 0;
964 }
965 DbpString("Stopped");
966 if (ledcontrol) LED_A_OFF();
967 }
968
969 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
970 {
971 uint8_t *dest = BigBuf_get_addr();
972 int idx=0;
973 uint32_t code=0, code2=0;
974 uint8_t version=0;
975 uint8_t facilitycode=0;
976 uint16_t number=0;
977 uint8_t crc = 0;
978 uint16_t calccrc = 0;
979 // Configure to go in 125Khz listen mode
980 LFSetupFPGAForADC(95, true);
981
982 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
983 WDT_HIT();
984 if (ledcontrol) LED_A_ON();
985 DoAcquisition_default(-1,true);
986 //fskdemod and get start index
987 WDT_HIT();
988 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
989 if (idx<0) continue;
990 //valid tag found
991
992 //Index map
993 //0 10 20 30 40 50 60
994 //| | | | | | |
995 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
996 //-----------------------------------------------------------------------------
997 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
998 //
999 //Checksum:
1000 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1001 //preamble F0 E0 01 03 B6 75
1002 // How to calc checksum,
1003 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1004 // F0 + E0 + 01 + 03 + B6 = 28A
1005 // 28A & FF = 8A
1006 // FF - 8A = 75
1007 // Checksum: 0x75
1008 //XSF(version)facility:codeone+codetwo
1009 //Handle the data
1010 if(findone){ //only print binary if we are doing one
1011 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1012 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1013 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1014 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1015 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1016 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1017 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1018 }
1019 code = bytebits_to_byte(dest+idx,32);
1020 code2 = bytebits_to_byte(dest+idx+32,32);
1021 version = bytebits_to_byte(dest+idx+27,8); //14,4
1022 facilitycode = bytebits_to_byte(dest+idx+18,8);
1023 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1024
1025 crc = bytebits_to_byte(dest+idx+54,8);
1026 for (uint8_t i=1; i<6; ++i)
1027 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1028 calccrc &= 0xff;
1029 calccrc = 0xff - calccrc;
1030
1031 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1032
1033 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1034 // if we're only looking for one tag
1035 if (findone){
1036 if (ledcontrol) LED_A_OFF();
1037 *high=code;
1038 *low=code2;
1039 return;
1040 }
1041 code=code2=0;
1042 version=facilitycode=0;
1043 number=0;
1044 idx=0;
1045
1046 WDT_HIT();
1047 }
1048 DbpString("Stopped");
1049 if (ledcontrol) LED_A_OFF();
1050 }
1051
1052 /*------------------------------
1053 * T5555/T5557/T5567/T5577 routines
1054 *------------------------------
1055 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1056 *
1057 * Relevant communication times in microsecond
1058 * To compensate antenna falling times shorten the write times
1059 * and enlarge the gap ones.
1060 * Q5 tags seems to have issues when these values changes.
1061 */
1062
1063 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1064 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1065 #define WRITE_0 16*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1066 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1067 #define READ_GAP 15*8
1068
1069 // VALUES TAKEN FROM EM4x function: SendForward
1070 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1071 // WRITE_GAP = 128; (16*8)
1072 // WRITE_1 = 256 32*8; (32*8)
1073
1074 // These timings work for 4469/4269/4305 (with the 55*8 above)
1075 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1076
1077 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1078 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1079 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1080 // T0 = TIMER_CLOCK1 / 125000 = 192
1081 // 1 Cycle = 8 microseconds(us) == 1 field clock
1082
1083 void TurnReadLFOn(int delay) {
1084 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1085 // Give it a bit of time for the resonant antenna to settle.
1086
1087 // measure antenna strength.
1088 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1089 // where to save it
1090
1091 SpinDelayUs(delay);
1092 }
1093
1094 // Write one bit to card
1095 void T55xxWriteBit(int bit) {
1096 if (!bit)
1097 TurnReadLFOn(WRITE_0);
1098 else
1099 TurnReadLFOn(WRITE_1);
1100 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1101 SpinDelayUs(WRITE_GAP);
1102 }
1103
1104 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1105 void T55xxResetRead(void) {
1106 LED_A_ON();
1107 //clear buffer now so it does not interfere with timing later
1108 BigBuf_Clear_ext(false);
1109
1110 // Set up FPGA, 125kHz
1111 LFSetupFPGAForADC(95, true);
1112
1113 // Trigger T55x7 in mode.
1114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1115 SpinDelayUs(START_GAP);
1116
1117 // reset tag - op code 00
1118 T55xxWriteBit(0);
1119 T55xxWriteBit(0);
1120
1121 // Turn field on to read the response
1122 TurnReadLFOn(READ_GAP);
1123
1124 // Acquisition
1125 doT55x7Acquisition(BigBuf_max_traceLen());
1126
1127 // Turn the field off
1128 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1129 cmd_send(CMD_ACK,0,0,0,0,0);
1130 LED_A_OFF();
1131 }
1132
1133 // Write one card block in page 0, no lock
1134 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1135 LED_A_ON();
1136 bool PwdMode = arg & 0x1;
1137 uint8_t Page = (arg & 0x2)>>1;
1138 uint32_t i = 0;
1139
1140 // Set up FPGA, 125kHz
1141 LFSetupFPGAForADC(95, true);
1142
1143 // Trigger T55x7 in mode.
1144 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1145 SpinDelayUs(START_GAP);
1146
1147 // Opcode 10
1148 T55xxWriteBit(1);
1149 T55xxWriteBit(Page); //Page 0
1150 if (PwdMode){
1151 // Send Pwd
1152 for (i = 0x80000000; i != 0; i >>= 1)
1153 T55xxWriteBit(Pwd & i);
1154 }
1155 // Send Lock bit
1156 T55xxWriteBit(0);
1157
1158 // Send Data
1159 for (i = 0x80000000; i != 0; i >>= 1)
1160 T55xxWriteBit(Data & i);
1161
1162 // Send Block number
1163 for (i = 0x04; i != 0; i >>= 1)
1164 T55xxWriteBit(Block & i);
1165
1166 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1167 // so wait a little more)
1168 TurnReadLFOn(20 * 1000);
1169 //could attempt to do a read to confirm write took
1170 // as the tag should repeat back the new block
1171 // until it is reset, but to confirm it we would
1172 // need to know the current block 0 config mode
1173
1174 // turn field off
1175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1176 LED_A_OFF();
1177 }
1178
1179 // Write one card block in page 0, no lock
1180 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1181 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1182 cmd_send(CMD_ACK,0,0,0,0,0);
1183 }
1184
1185 // Read one card block in page [page]
1186 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1187 LED_A_ON();
1188 bool PwdMode = arg0 & 0x1;
1189 uint8_t Page = (arg0 & 0x2) >> 1;
1190 uint32_t i = 0;
1191 bool RegReadMode = (Block == 0xFF);
1192
1193 //clear buffer now so it does not interfere with timing later
1194 BigBuf_Clear_ext(false);
1195
1196 //make sure block is at max 7
1197 Block &= 0x7;
1198
1199 // Set up FPGA, 125kHz to power up the tag
1200 LFSetupFPGAForADC(95, true);
1201
1202 // Trigger T55x7 Direct Access Mode with start gap
1203 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1204 SpinDelayUs(START_GAP);
1205
1206 // Opcode 1[page]
1207 T55xxWriteBit(1);
1208 T55xxWriteBit(Page); //Page 0
1209
1210 if (PwdMode){
1211 // Send Pwd
1212 for (i = 0x80000000; i != 0; i >>= 1)
1213 T55xxWriteBit(Pwd & i);
1214 }
1215 // Send a zero bit separation
1216 T55xxWriteBit(0);
1217
1218 // Send Block number (if direct access mode)
1219 if (!RegReadMode)
1220 for (i = 0x04; i != 0; i >>= 1)
1221 T55xxWriteBit(Block & i);
1222
1223 // Turn field on to read the response
1224 TurnReadLFOn(READ_GAP);
1225
1226 // Acquisition
1227 doT55x7Acquisition(12000);
1228
1229 // Turn the field off
1230 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1231 cmd_send(CMD_ACK,0,0,0,0,0);
1232 LED_A_OFF();
1233 }
1234
1235 void T55xxWakeUp(uint32_t Pwd){
1236 LED_B_ON();
1237 uint32_t i = 0;
1238
1239 // Set up FPGA, 125kHz
1240 LFSetupFPGAForADC(95, true);
1241
1242 // Trigger T55x7 Direct Access Mode
1243 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1244 SpinDelayUs(START_GAP);
1245
1246 // Opcode 10
1247 T55xxWriteBit(1);
1248 T55xxWriteBit(0); //Page 0
1249
1250 // Send Pwd
1251 for (i = 0x80000000; i != 0; i >>= 1)
1252 T55xxWriteBit(Pwd & i);
1253
1254 // Turn and leave field on to let the begin repeating transmission
1255 TurnReadLFOn(20*1000);
1256 }
1257
1258 /*-------------- Cloning routines -----------*/
1259
1260 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1261 // write last block first and config block last (if included)
1262 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1263 T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
1264 }
1265
1266 // Copy HID id to card and setup block 0 config
1267 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1268 uint32_t data[] = {0,0,0,0,0,0,0};
1269 uint8_t last_block = 0;
1270
1271 if (longFMT){
1272 // Ensure no more than 84 bits supplied
1273 if (hi2>0xFFFFF) {
1274 DbpString("Tags can only have 84 bits.");
1275 return;
1276 }
1277 // Build the 6 data blocks for supplied 84bit ID
1278 last_block = 6;
1279 // load preamble (1D) & long format identifier (9E manchester encoded)
1280 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1281 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1282 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1283 data[3] = manchesterEncode2Bytes(hi >> 16);
1284 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1285 data[5] = manchesterEncode2Bytes(lo >> 16);
1286 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1287 } else {
1288 // Ensure no more than 44 bits supplied
1289 if (hi>0xFFF) {
1290 DbpString("Tags can only have 44 bits.");
1291 return;
1292 }
1293 // Build the 3 data blocks for supplied 44bit ID
1294 last_block = 3;
1295 // load preamble
1296 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1297 data[2] = manchesterEncode2Bytes(lo >> 16);
1298 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1299 }
1300 // load chip config block
1301 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1302
1303 //TODO add selection of chip for Q5 or T55x7
1304 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1305
1306 LED_D_ON();
1307 // Program the data blocks for supplied ID
1308 // and the block 0 for HID format
1309 WriteT55xx(data, 0, last_block+1);
1310
1311 LED_D_OFF();
1312
1313 DbpString("DONE!");
1314 }
1315
1316 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1317 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1318 //TODO add selection of chip for Q5 or T55x7
1319 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1320
1321 LED_D_ON();
1322 // Program the data blocks for supplied ID
1323 // and the block 0 config
1324 WriteT55xx(data, 0, 3);
1325
1326 LED_D_OFF();
1327
1328 DbpString("DONE!");
1329 }
1330
1331 // Clone Indala 64-bit tag by UID to T55x7
1332 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1333 //Program the 2 data blocks for supplied 64bit UID
1334 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1335 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1336 //TODO add selection of chip for Q5 or T55x7
1337 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1338
1339 WriteT55xx(data, 0, 3);
1340 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1341 // T5567WriteBlock(0x603E1042,0);
1342 DbpString("DONE!");
1343 }
1344 // Clone Indala 224-bit tag by UID to T55x7
1345 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1346 //Program the 7 data blocks for supplied 224bit UID
1347 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1348 // and the block 0 for Indala224 format
1349 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1350 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1351 //TODO add selection of chip for Q5 or T55x7
1352 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1353 WriteT55xx(data, 0, 8);
1354 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1355 // T5567WriteBlock(0x603E10E2,0);
1356 DbpString("DONE!");
1357 }
1358 // clone viking tag to T55xx
1359 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1360 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1361 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1362 // Program the data blocks for supplied ID and the block 0 config
1363 WriteT55xx(data, 0, 3);
1364 LED_D_OFF();
1365 cmd_send(CMD_ACK,0,0,0,0,0);
1366 }
1367
1368 // Define 9bit header for EM410x tags
1369 #define EM410X_HEADER 0x1FF
1370 #define EM410X_ID_LENGTH 40
1371
1372 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1373 int i, id_bit;
1374 uint64_t id = EM410X_HEADER;
1375 uint64_t rev_id = 0; // reversed ID
1376 int c_parity[4]; // column parity
1377 int r_parity = 0; // row parity
1378 uint32_t clock = 0;
1379
1380 // Reverse ID bits given as parameter (for simpler operations)
1381 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1382 if (i < 32) {
1383 rev_id = (rev_id << 1) | (id_lo & 1);
1384 id_lo >>= 1;
1385 } else {
1386 rev_id = (rev_id << 1) | (id_hi & 1);
1387 id_hi >>= 1;
1388 }
1389 }
1390
1391 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1392 id_bit = rev_id & 1;
1393
1394 if (i % 4 == 0) {
1395 // Don't write row parity bit at start of parsing
1396 if (i)
1397 id = (id << 1) | r_parity;
1398 // Start counting parity for new row
1399 r_parity = id_bit;
1400 } else {
1401 // Count row parity
1402 r_parity ^= id_bit;
1403 }
1404
1405 // First elements in column?
1406 if (i < 4)
1407 // Fill out first elements
1408 c_parity[i] = id_bit;
1409 else
1410 // Count column parity
1411 c_parity[i % 4] ^= id_bit;
1412
1413 // Insert ID bit
1414 id = (id << 1) | id_bit;
1415 rev_id >>= 1;
1416 }
1417
1418 // Insert parity bit of last row
1419 id = (id << 1) | r_parity;
1420
1421 // Fill out column parity at the end of tag
1422 for (i = 0; i < 4; ++i)
1423 id = (id << 1) | c_parity[i];
1424
1425 // Add stop bit
1426 id <<= 1;
1427
1428 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1429 LED_D_ON();
1430
1431 // Write EM410x ID
1432 uint32_t data[] = {0, id>>32, id & 0xFFFFFFFF};
1433
1434 clock = (card & 0xFF00) >> 8;
1435 clock = (clock == 0) ? 64 : clock;
1436 Dbprintf("Clock rate: %d", clock);
1437 if (card & 0xFF) { //t55x7
1438 clock = GetT55xxClockBit(clock);
1439 if (clock == 0) {
1440 Dbprintf("Invalid clock rate: %d", clock);
1441 return;
1442 }
1443 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1444 } else { //t5555 (Q5)
1445 clock = (clock-2)>>1; //n = (RF-2)/2
1446 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1447 }
1448
1449 WriteT55xx(data, 0, 3);
1450
1451 LED_D_OFF();
1452 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1453 (uint32_t)(id >> 32), (uint32_t)id);
1454 }
1455
1456 //-----------------------------------
1457 // EM4469 / EM4305 routines
1458 //-----------------------------------
1459 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1460 #define FWD_CMD_WRITE 0xA
1461 #define FWD_CMD_READ 0x9
1462 #define FWD_CMD_DISABLE 0x5
1463
1464 uint8_t forwardLink_data[64]; //array of forwarded bits
1465 uint8_t * forward_ptr; //ptr for forward message preparation
1466 uint8_t fwd_bit_sz; //forwardlink bit counter
1467 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1468
1469 //====================================================================
1470 // prepares command bits
1471 // see EM4469 spec
1472 //====================================================================
1473 //--------------------------------------------------------------------
1474 // VALUES TAKEN FROM EM4x function: SendForward
1475 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1476 // WRITE_GAP = 128; (16*8)
1477 // WRITE_1 = 256 32*8; (32*8)
1478
1479 // These timings work for 4469/4269/4305 (with the 55*8 above)
1480 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1481
1482 uint8_t Prepare_Cmd( uint8_t cmd ) {
1483
1484 *forward_ptr++ = 0; //start bit
1485 *forward_ptr++ = 0; //second pause for 4050 code
1486
1487 *forward_ptr++ = cmd;
1488 cmd >>= 1;
1489 *forward_ptr++ = cmd;
1490 cmd >>= 1;
1491 *forward_ptr++ = cmd;
1492 cmd >>= 1;
1493 *forward_ptr++ = cmd;
1494
1495 return 6; //return number of emited bits
1496 }
1497
1498 //====================================================================
1499 // prepares address bits
1500 // see EM4469 spec
1501 //====================================================================
1502 uint8_t Prepare_Addr( uint8_t addr ) {
1503
1504 register uint8_t line_parity;
1505
1506 uint8_t i;
1507 line_parity = 0;
1508 for(i=0;i<6;i++) {
1509 *forward_ptr++ = addr;
1510 line_parity ^= addr;
1511 addr >>= 1;
1512 }
1513
1514 *forward_ptr++ = (line_parity & 1);
1515
1516 return 7; //return number of emited bits
1517 }
1518
1519 //====================================================================
1520 // prepares data bits intreleaved with parity bits
1521 // see EM4469 spec
1522 //====================================================================
1523 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1524
1525 register uint8_t line_parity;
1526 register uint8_t column_parity;
1527 register uint8_t i, j;
1528 register uint16_t data;
1529
1530 data = data_low;
1531 column_parity = 0;
1532
1533 for(i=0; i<4; i++) {
1534 line_parity = 0;
1535 for(j=0; j<8; j++) {
1536 line_parity ^= data;
1537 column_parity ^= (data & 1) << j;
1538 *forward_ptr++ = data;
1539 data >>= 1;
1540 }
1541 *forward_ptr++ = line_parity;
1542 if(i == 1)
1543 data = data_hi;
1544 }
1545
1546 for(j=0; j<8; j++) {
1547 *forward_ptr++ = column_parity;
1548 column_parity >>= 1;
1549 }
1550 *forward_ptr = 0;
1551
1552 return 45; //return number of emited bits
1553 }
1554
1555 //====================================================================
1556 // Forward Link send function
1557 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1558 // fwd_bit_count set with number of bits to be sent
1559 //====================================================================
1560 void SendForward(uint8_t fwd_bit_count) {
1561
1562 fwd_write_ptr = forwardLink_data;
1563 fwd_bit_sz = fwd_bit_count;
1564
1565 LED_D_ON();
1566
1567 // Set up FPGA, 125kHz
1568 LFSetupFPGAForADC(95, true);
1569
1570 // force 1st mod pulse (start gap must be longer for 4305)
1571 fwd_bit_sz--; //prepare next bit modulation
1572 fwd_write_ptr++;
1573 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1574 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1575 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1576 SpinDelayUs(16*8); //16 cycles on (8us each)
1577
1578 // now start writting
1579 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1580 if(((*fwd_write_ptr++) & 1) == 1)
1581 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1582 else {
1583 //These timings work for 4469/4269/4305 (with the 55*8 above)
1584 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1585 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1586 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1587 SpinDelayUs(9*8); //16 cycles on (8us each)
1588 }
1589 }
1590 }
1591
1592 void EM4xLogin(uint32_t Password) {
1593
1594 uint8_t fwd_bit_count;
1595
1596 forward_ptr = forwardLink_data;
1597 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1598 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1599
1600 SendForward(fwd_bit_count);
1601
1602 //Wait for command to complete
1603 SpinDelay(20);
1604 }
1605
1606 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1607
1608 uint8_t fwd_bit_count;
1609 uint8_t *dest = BigBuf_get_addr();
1610 uint16_t bufsize = BigBuf_max_traceLen();
1611 uint32_t i = 0;
1612
1613 //clear buffer now so it does not interfere with timing later
1614 BigBuf_Clear_ext(false);
1615
1616 //If password mode do login
1617 if (PwdMode == 1) EM4xLogin(Pwd);
1618
1619 forward_ptr = forwardLink_data;
1620 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1621 fwd_bit_count += Prepare_Addr( Address );
1622
1623 // Connect the A/D to the peak-detected low-frequency path.
1624 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1625 // Now set up the SSC to get the ADC samples that are now streaming at us.
1626 FpgaSetupSsc();
1627
1628 SendForward(fwd_bit_count);
1629
1630 // Now do the acquisition
1631 i = 0;
1632 for(;;) {
1633 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1634 AT91C_BASE_SSC->SSC_THR = 0x43;
1635 }
1636 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1637 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1638 ++i;
1639 if (i >= bufsize) break;
1640 }
1641 }
1642
1643 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1644 cmd_send(CMD_ACK,0,0,0,0,0);
1645 LED_D_OFF();
1646 }
1647
1648 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1649
1650 uint8_t fwd_bit_count;
1651
1652 //If password mode do login
1653 if (PwdMode == 1) EM4xLogin(Pwd);
1654
1655 forward_ptr = forwardLink_data;
1656 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1657 fwd_bit_count += Prepare_Addr( Address );
1658 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1659
1660 SendForward(fwd_bit_count);
1661
1662 //Wait for write to complete
1663 SpinDelay(20);
1664 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1665 LED_D_OFF();
1666 }
Proxmark3 GIT tracking
Impressum, Datenschutz