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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../include/hitag2.h"
15 #include "../common/crc16.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19
20 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
21 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
22 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
23 // T0 = TIMER_CLOCK1 / 125000 = 192
24 #define T0 192
25
26 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
27 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
28
29 void LFSetupFPGAForADC(int divisor, bool lf_field)
30 {
31 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
32 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
33 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
34 else if (divisor == 0)
35 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
36 else
37 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
38
39 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
40
41 // Connect the A/D to the peak-detected low-frequency path.
42 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
43
44 // Give it a bit of time for the resonant antenna to settle.
45 SpinDelay(150);
46
47 // Now set up the SSC to get the ADC samples that are now streaming at us.
48 FpgaSetupSsc();
49 }
50
51 void AcquireRawAdcSamples125k(int divisor)
52 {
53 LFSetupFPGAForADC(divisor, true);
54 DoAcquisition125k();
55 }
56
57 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
58 {
59 LFSetupFPGAForADC(divisor, false);
60 DoAcquisition125k_threshold(trigger_threshold);
61 }
62
63 // split into two routines so we can avoid timing issues after sending commands //
64 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
65 {
66 uint8_t *dest = get_bigbufptr_recvrespbuf();
67 uint16_t i = 0;
68 memset(dest, 0x00, FREE_BUFFER_SIZE);
69
70 for(;;) {
71 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
72 AT91C_BASE_SSC->SSC_THR = 0x43;
73 LED_D_ON();
74 }
75 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
76 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
77 LED_D_OFF();
78 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
79 continue;
80 else
81 trigger_threshold = -1;
82 if (++i >= FREE_BUFFER_SIZE) break;
83 }
84 }
85 if (!silent){
86 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
87 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
88 }
89 }
90 void DoAcquisition125k_threshold(int trigger_threshold) {
91 DoAcquisition125k_internal(trigger_threshold, true);
92 }
93 void DoAcquisition125k() {
94 DoAcquisition125k_internal(-1, true);
95 }
96
97 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
98 {
99 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
100
101 /* Make sure the tag is reset */
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
103 SpinDelay(2500);
104
105 int divisor = 95; // 125 KHz
106 // see if 'h' was specified
107 if (command[strlen((char *) command) - 1] == 'h')
108 divisor = 88; // 134.8 KHz
109
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
111 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
112 // Give it a bit of time for the resonant antenna to settle.
113 SpinDelay(2000);
114
115 // Now set up the SSC to get the ADC samples that are now streaming at us.
116 FpgaSetupSsc();
117
118 // now modulate the reader field
119 while(*command != '\0' && *command != ' ') {
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121 LED_D_OFF();
122 SpinDelayUs(delay_off);
123 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
124
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
126 LED_D_ON();
127 if(*(command++) == '0')
128 SpinDelayUs(period_0);
129 else
130 SpinDelayUs(period_1);
131 }
132 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
133 LED_D_OFF();
134 SpinDelayUs(delay_off);
135 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
136 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
137
138 // now do the read
139 DoAcquisition125k(-1);
140 }
141
142 /* blank r/w tag data stream
143 ...0000000000000000 01111111
144 1010101010101010101010101010101010101010101010101010101010101010
145 0011010010100001
146 01111111
147 101010101010101[0]000...
148
149 [5555fe852c5555555555555555fe0000]
150 */
151 void ReadTItag(void)
152 {
153 // some hardcoded initial params
154 // when we read a TI tag we sample the zerocross line at 2Mhz
155 // TI tags modulate a 1 as 16 cycles of 123.2Khz
156 // TI tags modulate a 0 as 16 cycles of 134.2Khz
157 #define FSAMPLE 2000000
158 #define FREQLO 123200
159 #define FREQHI 134200
160
161 signed char *dest = (signed char *)BigBuf;
162 int n = sizeof(BigBuf);
163 // int *dest = GraphBuffer;
164 // int n = GraphTraceLen;
165
166 // 128 bit shift register [shift3:shift2:shift1:shift0]
167 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
168
169 int i, cycles=0, samples=0;
170 // how many sample points fit in 16 cycles of each frequency
171 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
172 // when to tell if we're close enough to one freq or another
173 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
174
175 // TI tags charge at 134.2Khz
176 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
177 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
178
179 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
180 // connects to SSP_DIN and the SSP_DOUT logic level controls
181 // whether we're modulating the antenna (high)
182 // or listening to the antenna (low)
183 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
184
185 // get TI tag data into the buffer
186 AcquireTiType();
187
188 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
189
190 for (i=0; i<n-1; i++) {
191 // count cycles by looking for lo to hi zero crossings
192 if ( (dest[i]<0) && (dest[i+1]>0) ) {
193 cycles++;
194 // after 16 cycles, measure the frequency
195 if (cycles>15) {
196 cycles=0;
197 samples=i-samples; // number of samples in these 16 cycles
198
199 // TI bits are coming to us lsb first so shift them
200 // right through our 128 bit right shift register
201 shift0 = (shift0>>1) | (shift1 << 31);
202 shift1 = (shift1>>1) | (shift2 << 31);
203 shift2 = (shift2>>1) | (shift3 << 31);
204 shift3 >>= 1;
205
206 // check if the cycles fall close to the number
207 // expected for either the low or high frequency
208 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
209 // low frequency represents a 1
210 shift3 |= (1<<31);
211 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
212 // high frequency represents a 0
213 } else {
214 // probably detected a gay waveform or noise
215 // use this as gaydar or discard shift register and start again
216 shift3 = shift2 = shift1 = shift0 = 0;
217 }
218 samples = i;
219
220 // for each bit we receive, test if we've detected a valid tag
221
222 // if we see 17 zeroes followed by 6 ones, we might have a tag
223 // remember the bits are backwards
224 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
225 // if start and end bytes match, we have a tag so break out of the loop
226 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
227 cycles = 0xF0B; //use this as a flag (ugly but whatever)
228 break;
229 }
230 }
231 }
232 }
233 }
234
235 // if flag is set we have a tag
236 if (cycles!=0xF0B) {
237 DbpString("Info: No valid tag detected.");
238 } else {
239 // put 64 bit data into shift1 and shift0
240 shift0 = (shift0>>24) | (shift1 << 8);
241 shift1 = (shift1>>24) | (shift2 << 8);
242
243 // align 16 bit crc into lower half of shift2
244 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
245
246 // if r/w tag, check ident match
247 if ( shift3&(1<<15) ) {
248 DbpString("Info: TI tag is rewriteable");
249 // only 15 bits compare, last bit of ident is not valid
250 if ( ((shift3>>16)^shift0)&0x7fff ) {
251 DbpString("Error: Ident mismatch!");
252 } else {
253 DbpString("Info: TI tag ident is valid");
254 }
255 } else {
256 DbpString("Info: TI tag is readonly");
257 }
258
259 // WARNING the order of the bytes in which we calc crc below needs checking
260 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
261 // bytes in reverse or something
262 // calculate CRC
263 uint32_t crc=0;
264
265 crc = update_crc16(crc, (shift0)&0xff);
266 crc = update_crc16(crc, (shift0>>8)&0xff);
267 crc = update_crc16(crc, (shift0>>16)&0xff);
268 crc = update_crc16(crc, (shift0>>24)&0xff);
269 crc = update_crc16(crc, (shift1)&0xff);
270 crc = update_crc16(crc, (shift1>>8)&0xff);
271 crc = update_crc16(crc, (shift1>>16)&0xff);
272 crc = update_crc16(crc, (shift1>>24)&0xff);
273
274 Dbprintf("Info: Tag data: %x%08x, crc=%x",
275 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
276 if (crc != (shift2&0xffff)) {
277 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
278 } else {
279 DbpString("Info: CRC is good");
280 }
281 }
282 }
283
284 void WriteTIbyte(uint8_t b)
285 {
286 int i = 0;
287
288 // modulate 8 bits out to the antenna
289 for (i=0; i<8; i++)
290 {
291 if (b&(1<<i)) {
292 // stop modulating antenna
293 SHORT_COIL();
294 SpinDelayUs(1000);
295 // modulate antenna
296 OPEN_COIL();
297 SpinDelayUs(1000);
298 } else {
299 // stop modulating antenna
300 SHORT_COIL();
301 SpinDelayUs(300);
302 // modulate antenna
303 OPEN_COIL();
304 SpinDelayUs(1700);
305 }
306 }
307 }
308
309 void AcquireTiType(void)
310 {
311 int i, j, n;
312 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
313 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
314 #define TIBUFLEN 1250
315
316 // clear buffer
317 memset(BigBuf,0,sizeof(BigBuf));
318
319 // Set up the synchronous serial port
320 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
321 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
322
323 // steal this pin from the SSP and use it to control the modulation
324 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
325 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
326
327 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
328 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
329
330 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
331 // 48/2 = 24 MHz clock must be divided by 12
332 AT91C_BASE_SSC->SSC_CMR = 12;
333
334 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
335 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
336 AT91C_BASE_SSC->SSC_TCMR = 0;
337 AT91C_BASE_SSC->SSC_TFMR = 0;
338
339 LED_D_ON();
340
341 // modulate antenna
342 HIGH(GPIO_SSC_DOUT);
343
344 // Charge TI tag for 50ms.
345 SpinDelay(50);
346
347 // stop modulating antenna and listen
348 LOW(GPIO_SSC_DOUT);
349
350 LED_D_OFF();
351
352 i = 0;
353 for(;;) {
354 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
355 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
356 i++; if(i >= TIBUFLEN) break;
357 }
358 WDT_HIT();
359 }
360
361 // return stolen pin to SSP
362 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
363 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
364
365 char *dest = (char *)BigBuf;
366 n = TIBUFLEN*32;
367 // unpack buffer
368 for (i=TIBUFLEN-1; i>=0; i--) {
369 for (j=0; j<32; j++) {
370 if(BigBuf[i] & (1 << j)) {
371 dest[--n] = 1;
372 } else {
373 dest[--n] = -1;
374 }
375 }
376 }
377 }
378
379 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
380 // if crc provided, it will be written with the data verbatim (even if bogus)
381 // if not provided a valid crc will be computed from the data and written.
382 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
383 {
384 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
385 if(crc == 0) {
386 crc = update_crc16(crc, (idlo)&0xff);
387 crc = update_crc16(crc, (idlo>>8)&0xff);
388 crc = update_crc16(crc, (idlo>>16)&0xff);
389 crc = update_crc16(crc, (idlo>>24)&0xff);
390 crc = update_crc16(crc, (idhi)&0xff);
391 crc = update_crc16(crc, (idhi>>8)&0xff);
392 crc = update_crc16(crc, (idhi>>16)&0xff);
393 crc = update_crc16(crc, (idhi>>24)&0xff);
394 }
395 Dbprintf("Writing to tag: %x%08x, crc=%x",
396 (unsigned int) idhi, (unsigned int) idlo, crc);
397
398 // TI tags charge at 134.2Khz
399 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
400 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
401 // connects to SSP_DIN and the SSP_DOUT logic level controls
402 // whether we're modulating the antenna (high)
403 // or listening to the antenna (low)
404 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
405 LED_A_ON();
406
407 // steal this pin from the SSP and use it to control the modulation
408 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
409 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
410
411 // writing algorithm:
412 // a high bit consists of a field off for 1ms and field on for 1ms
413 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
414 // initiate a charge time of 50ms (field on) then immediately start writing bits
415 // start by writing 0xBB (keyword) and 0xEB (password)
416 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
417 // finally end with 0x0300 (write frame)
418 // all data is sent lsb firts
419 // finish with 15ms programming time
420
421 // modulate antenna
422 HIGH(GPIO_SSC_DOUT);
423 SpinDelay(50); // charge time
424
425 WriteTIbyte(0xbb); // keyword
426 WriteTIbyte(0xeb); // password
427 WriteTIbyte( (idlo )&0xff );
428 WriteTIbyte( (idlo>>8 )&0xff );
429 WriteTIbyte( (idlo>>16)&0xff );
430 WriteTIbyte( (idlo>>24)&0xff );
431 WriteTIbyte( (idhi )&0xff );
432 WriteTIbyte( (idhi>>8 )&0xff );
433 WriteTIbyte( (idhi>>16)&0xff );
434 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
435 WriteTIbyte( (crc )&0xff ); // crc lo
436 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
437 WriteTIbyte(0x00); // write frame lo
438 WriteTIbyte(0x03); // write frame hi
439 HIGH(GPIO_SSC_DOUT);
440 SpinDelay(50); // programming time
441
442 LED_A_OFF();
443
444 // get TI tag data into the buffer
445 AcquireTiType();
446
447 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
448 DbpString("Now use tiread to check");
449 }
450
451
452
453 // PIO_CODR = Clear Output Data Register
454 // PIO_SODR = Set Output Data Register
455 //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
456 //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
457 void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol)
458 {
459 LED_D_ON();
460
461 uint16_t i = 0;
462 uint8_t send = 0;
463
464 //int overflow = 0;
465 uint8_t *buf = (uint8_t *)BigBuf;
466
467 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
468 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
469 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
470 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
471 RELAY_OFF();
472
473 // Configure output pin that is connected to the FPGA (for modulating)
474 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
475 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
476
477 SHORT_COIL();
478
479 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
480 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
481
482 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
483 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
484 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
485
486 // Disable timer during configuration
487 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
488
489 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
490 // external trigger rising edge, load RA on rising edge of TIOA.
491 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
492
493 // Enable and reset counter
494 //AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
495 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
496
497 while(!BUTTON_PRESS()) {
498 WDT_HIT();
499
500 // Receive frame, watch for at most T0*EOF periods
501 while (AT91C_BASE_TC1->TC_CV < T0 * 55) {
502
503 // Check if rising edge in modulation is detected
504 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
505 // Retrieve the new timing values
506 //int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
507 //Dbprintf("Timing value - %d %d", ra, overflow);
508 //overflow = 0;
509
510 // Reset timer every frame, we have to capture the last edge for timing
511 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
512 send = 1;
513
514 LED_B_ON();
515 }
516 }
517
518 if ( send ) {
519 // Disable timer 1 with external trigger to avoid triggers during our own modulation
520 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
521
522 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
523 // not that since the clock counts since the rising edge, but T_Wait1 is
524 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
525 // periods. The gap time T_Low varies (4..10). All timer values are in
526 // terms of T0 units
527 while(AT91C_BASE_TC0->TC_CV < T0 * 16 );
528
529 // datat kommer in som 1 bit för varje position i arrayn
530 for(i = 0; i < period; ++i) {
531
532 // Reset clock for the next bit
533 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
534
535 if ( buf[i] > 0 )
536 HIGH(GPIO_SSC_DOUT);
537 else
538 LOW(GPIO_SSC_DOUT);
539
540 while(AT91C_BASE_TC0->TC_CV < T0 * 1 );
541 }
542 // Drop modulation
543 LOW(GPIO_SSC_DOUT);
544
545 // Enable and reset external trigger in timer for capturing future frames
546 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
547 LED_B_OFF();
548 }
549
550 send = 0;
551
552 // Save the timer overflow, will be 0 when frame was received
553 //overflow += (AT91C_BASE_TC1->TC_CV/T0);
554
555 // Reset the timer to restart while-loop that receives frames
556 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
557 }
558
559 LED_B_OFF();
560 LED_D_OFF();
561 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
562 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
563 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
564
565 DbpString("Sim Stopped");
566 }
567
568
569 void SimulateTagLowFrequencyA(int len, int gap)
570 {
571 //Dbprintf("LEN %d || Gap %d",len, gap);
572
573 uint8_t *buf = (uint8_t *)BigBuf;
574
575 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
576 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
577 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE); // new izsh toggle mode!
578
579 // Connect the A/D to the peak-detected low-frequency path.
580 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
581
582 // Now set up the SSC to get the ADC samples that are now streaming at us.
583 FpgaSetupSsc();
584 SpinDelay(5);
585
586 AT91C_BASE_SSC->SSC_THR = 0x00;
587
588 int i = 0;
589 while(!BUTTON_PRESS()) {
590 WDT_HIT();
591 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
592
593 if ( buf[i] > 0 )
594 AT91C_BASE_SSC->SSC_THR = 0x43;
595 else
596 AT91C_BASE_SSC->SSC_THR = 0x00;
597
598 ++i;
599 LED_A_ON();
600 if (i >= len){
601 i = 0;
602 }
603 }
604
605 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
606 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
607 (void)r;
608 LED_A_OFF();
609 }
610 }
611 DbpString("lf simulate stopped");
612 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
613 }
614
615 #define DEBUG_FRAME_CONTENTS 1
616 void SimulateTagLowFrequencyBidir(int divisor, int t0)
617 {
618 }
619
620 // compose fc/8 fc/10 waveform
621 static void fc(int c, uint16_t *n) {
622 uint8_t *dest = (uint8_t *)BigBuf;
623 int idx;
624
625 // for when we want an fc8 pattern every 4 logical bits
626 if(c==0) {
627 dest[((*n)++)]=1;
628 dest[((*n)++)]=1;
629 dest[((*n)++)]=0;
630 dest[((*n)++)]=0;
631 dest[((*n)++)]=0;
632 dest[((*n)++)]=0;
633 dest[((*n)++)]=0;
634 dest[((*n)++)]=0;
635 }
636 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
637 if(c==8) {
638 for (idx=0; idx<6; idx++) {
639 dest[((*n)++)]=1;
640 dest[((*n)++)]=1;
641 dest[((*n)++)]=0;
642 dest[((*n)++)]=0;
643 dest[((*n)++)]=0;
644 dest[((*n)++)]=0;
645 dest[((*n)++)]=0;
646 dest[((*n)++)]=0;
647 }
648 }
649
650 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
651 if(c==10) {
652 for (idx=0; idx<5; idx++) {
653 dest[((*n)++)]=1;
654 dest[((*n)++)]=1;
655 dest[((*n)++)]=1;
656 dest[((*n)++)]=0;
657 dest[((*n)++)]=0;
658 dest[((*n)++)]=0;
659 dest[((*n)++)]=0;
660 dest[((*n)++)]=0;
661 dest[((*n)++)]=0;
662 dest[((*n)++)]=0;
663 }
664 }
665 }
666
667 // prepare a waveform pattern in the buffer based on the ID given then
668 // simulate a HID tag until the button is pressed
669 void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol)
670 {
671 uint16_t n=0, i=0;
672 /*
673 HID tag bitstream format
674 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
675 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
676 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
677 A fc8 is inserted before every 4 bits
678 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
679 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
680 */
681
682 if (hi>0xFFF) {
683 DbpString("Tags can only have 44 bits.");
684 return;
685 }
686 fc(0,&n);
687 // special start of frame marker containing invalid bit sequences
688 fc(8, &n); fc(8, &n); // invalid
689 fc(8, &n); fc(10, &n); // logical 0
690 fc(10, &n); fc(10, &n); // invalid
691 fc(8, &n); fc(10, &n); // logical 0
692
693 WDT_HIT();
694 // manchester encode bits 43 to 32
695 for (i=11; i>=0; i--) {
696 if ((i%4)==3) fc(0,&n);
697 if ((hi>>i)&1) {
698 fc(10, &n); fc(8, &n); // low-high transition
699 } else {
700 fc(8, &n); fc(10, &n); // high-low transition
701 }
702 }
703
704 WDT_HIT();
705 // manchester encode bits 31 to 0
706 for (i=31; i>=0; i--) {
707 if ((i%4)==3) fc(0,&n);
708 if ((lo>>i)&1) {
709 fc(10, &n); fc(8, &n); // low-high transition
710 } else {
711 fc(8, &n); fc(10, &n); // high-low transition
712 }
713 }
714
715 if (ledcontrol)
716 LED_A_ON();
717
718 SimulateTagLowFrequency(n, 0, ledcontrol);
719
720 if (ledcontrol)
721 LED_A_OFF();
722 }
723
724 size_t fsk_demod(uint8_t * dest, size_t size)
725 {
726 uint32_t last_transition = 0;
727 uint32_t idx = 1;
728
729 // we don't care about actual value, only if it's more or less than a
730 // threshold essentially we capture zero crossings for later analysis
731 uint8_t threshold_value = 127;
732
733 // sync to first lo-hi transition, and threshold
734
735 //Need to threshold first sample
736 dest[0] = (dest[0] < threshold_value) ? 0 : 1;
737
738 size_t numBits = 0;
739 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
740 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
741 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
742 for(idx = 1; idx < size; idx++) {
743 // threshold current value
744 dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;
745
746 // Check for 0->1 transition
747 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
748
749 dest[numBits] = (idx-last_transition < 9) ? 1 : 0;
750 last_transition = idx;
751 numBits++;
752 }
753 }
754 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
755 }
756
757
758 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits, uint8_t invert )
759 {
760 uint8_t lastval=dest[0];
761 uint32_t idx=0;
762 size_t numBits=0;
763 uint32_t n=1;
764
765 for( idx=1; idx < size; idx++) {
766
767 if (dest[idx]==lastval) {
768 n++;
769 continue;
770 }
771 //if lastval was 1, we have a 1->0 crossing
772 if ( dest[idx-1] ) {
773 n=(n+1) / h2l_crossing_value;
774 } else {// 0->1 crossing
775 n=(n+1) / l2h_crossing_value;
776 }
777 if (n == 0) n = 1;
778
779 if(n < maxConsequtiveBits)
780 {
781 if ( invert==0)
782 memset(dest+numBits, dest[idx-1] , n);
783 else
784 memset(dest+numBits, dest[idx-1]^1 , n);
785
786 numBits += n;
787 }
788 n=0;
789 lastval=dest[idx];
790 }//end for
791
792 return numBits;
793
794 }
795 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
796 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
797 {
798 uint8_t *dest = get_bigbufptr_recvrespbuf();
799
800 size_t size=0,idx=0; //, found=0;
801 uint32_t hi2=0, hi=0, lo=0;
802
803 // Configure to go in 125Khz listen mode
804 LFSetupFPGAForADC(0, true);
805
806 while(!BUTTON_PRESS()) {
807
808 WDT_HIT();
809 if (ledcontrol) LED_A_ON();
810
811 DoAcquisition125k_internal(-1,true);
812
813 // FSK demodulator
814 size = fsk_demod(dest, FREE_BUFFER_SIZE);
815
816 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
817 // 1->0 : fc/8 in sets of 6 (RF/50 / 8 = 6.25)
818 // 0->1 : fc/10 in sets of 5 (RF/50 / 10= 5)
819 // do not invert
820 size = aggregate_bits(dest,size, 6,5,5,0);
821
822 WDT_HIT();
823
824 // final loop, go over previously decoded manchester data and decode into usable tag ID
825 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
826 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
827 int numshifts = 0;
828 idx = 0;
829 while( idx + sizeof(frame_marker_mask) < size) {
830 // search for a start of frame marker
831 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
832 { // frame marker found
833 idx+=sizeof(frame_marker_mask);
834
835 while(dest[idx] != dest[idx+1] && idx < size-2)
836 {
837 // Keep going until next frame marker (or error)
838 // Shift in a bit. Start by shifting high registers
839 hi2=(hi2<<1)|(hi>>31);
840 hi=(hi<<1)|(lo>>31);
841 //Then, shift in a 0 or one into low
842 if (dest[idx] && !dest[idx+1]) // 1 0
843 lo=(lo<<1)|0;
844 else // 0 1
845 lo=(lo<<1)|
846 1;
847 numshifts ++;
848 idx += 2;
849 }
850 //Dbprintf("Num shifts: %d ", numshifts);
851 // Hopefully, we read a tag and hit upon the next frame marker
852 if(idx + sizeof(frame_marker_mask) < size)
853 {
854 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
855 {
856 if (hi2 != 0){ //extra large HID tags
857 Dbprintf("TAG ID: %x%08x%08x (%d)",
858 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
859 }
860 else { //standard HID tags <38 bits
861 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
862 uint8_t bitlen = 0;
863 uint32_t fc = 0;
864 uint32_t cardnum = 0;
865 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
866 uint32_t lo2=0;
867 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
868 uint8_t idx3 = 1;
869 while(lo2>1){ //find last bit set to 1 (format len bit)
870 lo2=lo2>>1;
871 idx3++;
872 }
873 bitlen =idx3+19;
874 fc =0;
875 cardnum=0;
876 if(bitlen==26){
877 cardnum = (lo>>1)&0xFFFF;
878 fc = (lo>>17)&0xFF;
879 }
880 if(bitlen==37){
881 cardnum = (lo>>1)&0x7FFFF;
882 fc = ((hi&0xF)<<12)|(lo>>20);
883 }
884 if(bitlen==34){
885 cardnum = (lo>>1)&0xFFFF;
886 fc= ((hi&1)<<15)|(lo>>17);
887 }
888 if(bitlen==35){
889 cardnum = (lo>>1)&0xFFFFF;
890 fc = ((hi&1)<<11)|(lo>>21);
891 }
892 }
893 else { //if bit 38 is not set then 37 bit format is used
894 bitlen= 37;
895 fc =0;
896 cardnum=0;
897 if(bitlen==37){
898 cardnum = (lo>>1)&0x7FFFF;
899 fc = ((hi&0xF)<<12)|(lo>>20);
900 }
901 }
902 //Dbprintf("TAG ID: %x%08x (%d)",
903 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
904 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
905 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
906 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
907 }
908 if (findone){
909 if (ledcontrol) LED_A_OFF();
910 return;
911 }
912 }
913 }
914 // reset
915 hi2 = hi = lo = 0;
916 numshifts = 0;
917 } else {
918 idx++;
919 }
920 }
921 WDT_HIT();
922
923 }
924 DbpString("Stopped");
925 if (ledcontrol) LED_A_OFF();
926 }
927
928 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
929 {
930 uint32_t num = 0;
931 for(int i = 0 ; i < numbits ; i++)
932 {
933 num = (num << 1) | (*src);
934 src++;
935 }
936 return num;
937 }
938
939
940 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
941 {
942 uint8_t *dest = (uint8_t *)BigBuf;
943 size_t size=0, idx=0;
944 uint32_t code=0, code2=0;
945 uint8_t isFinish = 0;
946
947 // Configure to go in 125Khz listen mode
948 LFSetupFPGAForADC(0, true);
949
950 while(!BUTTON_PRESS() & !isFinish) {
951
952 WDT_HIT();
953
954 if (ledcontrol) LED_A_ON();
955
956 DoAcquisition125k_internal(-1,true);
957 size = sizeof(BigBuf);
958
959 // FSK demodulator
960 size = fsk_demod(dest, size);
961 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
962 // 1->0 : fc/8 in sets of 7 (RF/64 / 8 = 8)
963 // 0->1 : fc/10 in sets of 6 (RF/64 / 10 = 6.4)
964 size = aggregate_bits(dest, size, 7,6,13,1); //13 max Consecutive should be ok as most 0s in row should be 10 for init seq - invert bits
965
966 //Index map
967 //0 10 20 30 40 50 60
968 //| | | | | | |
969 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
970 //-----------------------------------------------------------------------------
971 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
972 //
973 //XSF(version)facility:codeone+codetwo
974 //Handle the data
975
976 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
977
978 for( idx=0; idx < (size - 64); idx++) {
979 if ( memcmp(dest + idx, mask, sizeof(mask))==0) {
980 //frame marker found
981 if(findone){ //only print binary if we are doing one
982 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
983 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
984 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
985 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
986 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
987 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
988 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
989 }
990 code = bytebits_to_byte(dest+idx,32);
991 code2 = bytebits_to_byte(dest+idx+32,32);
992 short version = bytebits_to_byte(dest+idx+28,8); //14,4
993 char facilitycode = bytebits_to_byte(dest+idx+19,8) ;
994 uint16_t number = (bytebits_to_byte(dest+idx+37,8)<<8)|(bytebits_to_byte(dest+idx+46,8)); //36,9
995
996 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2);
997
998 // if we're only looking for one tag
999 if (findone){
1000 if (ledcontrol) LED_A_OFF();
1001 isFinish = 1;
1002 break;
1003 }
1004 }
1005 }
1006 WDT_HIT();
1007 }
1008 DbpString("Stopped");
1009 if (ledcontrol) LED_A_OFF();
1010 }
1011
1012 /*------------------------------
1013 * T5555/T5557/T5567 routines
1014 *------------------------------
1015 */
1016
1017 /* T55x7 configuration register definitions */
1018 #define T55x7_POR_DELAY 0x00000001
1019 #define T55x7_ST_TERMINATOR 0x00000008
1020 #define T55x7_PWD 0x00000010
1021 #define T55x7_MAXBLOCK_SHIFT 5
1022 #define T55x7_AOR 0x00000200
1023 #define T55x7_PSKCF_RF_2 0
1024 #define T55x7_PSKCF_RF_4 0x00000400
1025 #define T55x7_PSKCF_RF_8 0x00000800
1026 #define T55x7_MODULATION_DIRECT 0
1027 #define T55x7_MODULATION_PSK1 0x00001000
1028 #define T55x7_MODULATION_PSK2 0x00002000
1029 #define T55x7_MODULATION_PSK3 0x00003000
1030 #define T55x7_MODULATION_FSK1 0x00004000
1031 #define T55x7_MODULATION_FSK2 0x00005000
1032 #define T55x7_MODULATION_FSK1a 0x00006000
1033 #define T55x7_MODULATION_FSK2a 0x00007000
1034 #define T55x7_MODULATION_MANCHESTER 0x00008000
1035 #define T55x7_MODULATION_BIPHASE 0x00010000
1036 #define T55x7_BITRATE_RF_8 0
1037 #define T55x7_BITRATE_RF_16 0x00040000
1038 #define T55x7_BITRATE_RF_32 0x00080000
1039 #define T55x7_BITRATE_RF_40 0x000C0000
1040 #define T55x7_BITRATE_RF_50 0x00100000
1041 #define T55x7_BITRATE_RF_64 0x00140000
1042 #define T55x7_BITRATE_RF_100 0x00180000
1043 #define T55x7_BITRATE_RF_128 0x001C0000
1044
1045 /* T5555 (Q5) configuration register definitions */
1046 #define T5555_ST_TERMINATOR 0x00000001
1047 #define T5555_MAXBLOCK_SHIFT 0x00000001
1048 #define T5555_MODULATION_MANCHESTER 0
1049 #define T5555_MODULATION_PSK1 0x00000010
1050 #define T5555_MODULATION_PSK2 0x00000020
1051 #define T5555_MODULATION_PSK3 0x00000030
1052 #define T5555_MODULATION_FSK1 0x00000040
1053 #define T5555_MODULATION_FSK2 0x00000050
1054 #define T5555_MODULATION_BIPHASE 0x00000060
1055 #define T5555_MODULATION_DIRECT 0x00000070
1056 #define T5555_INVERT_OUTPUT 0x00000080
1057 #define T5555_PSK_RF_2 0
1058 #define T5555_PSK_RF_4 0x00000100
1059 #define T5555_PSK_RF_8 0x00000200
1060 #define T5555_USE_PWD 0x00000400
1061 #define T5555_USE_AOR 0x00000800
1062 #define T5555_BITRATE_SHIFT 12
1063 #define T5555_FAST_WRITE 0x00004000
1064 #define T5555_PAGE_SELECT 0x00008000
1065
1066 /*
1067 * Relevant times in microsecond
1068 * To compensate antenna falling times shorten the write times
1069 * and enlarge the gap ones.
1070 */
1071 #define START_GAP 30*8 // 10 - 50fc 250
1072 #define WRITE_GAP 20*8 // 8 - 30fc
1073 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
1074 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1075
1076 // VALUES TAKEN FROM EM4x function: SendForward
1077 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1078 // WRITE_GAP = 128; (16*8)
1079 // WRITE_1 = 256 32*8; (32*8)
1080
1081 // These timings work for 4469/4269/4305 (with the 55*8 above)
1082 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1083
1084 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1085
1086 // Write one bit to card
1087 void T55xxWriteBit(int bit)
1088 {
1089 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1090 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1091 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1092 if (!bit)
1093 SpinDelayUs(WRITE_0);
1094 else
1095 SpinDelayUs(WRITE_1);
1096 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1097 SpinDelayUs(WRITE_GAP);
1098 }
1099
1100 // Write one card block in page 0, no lock
1101 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1102 {
1103 uint32_t i = 0;
1104
1105 // Set up FPGA, 125kHz
1106 // Wait for config.. (192+8190xPOW)x8 == 67ms
1107 LFSetupFPGAForADC(0, true);
1108
1109 // Now start writting
1110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1111 SpinDelayUs(START_GAP);
1112
1113 // Opcode
1114 T55xxWriteBit(1);
1115 T55xxWriteBit(0); //Page 0
1116 if (PwdMode == 1){
1117 // Pwd
1118 for (i = 0x80000000; i != 0; i >>= 1)
1119 T55xxWriteBit(Pwd & i);
1120 }
1121 // Lock bit
1122 T55xxWriteBit(0);
1123
1124 // Data
1125 for (i = 0x80000000; i != 0; i >>= 1)
1126 T55xxWriteBit(Data & i);
1127
1128 // Block
1129 for (i = 0x04; i != 0; i >>= 1)
1130 T55xxWriteBit(Block & i);
1131
1132 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1133 // so wait a little more)
1134 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1135 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1136 SpinDelay(20);
1137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1138 }
1139
1140 // Read one card block in page 0
1141 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1142 {
1143 uint8_t *dest = get_bigbufptr_recvrespbuf();
1144 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1145 uint32_t i = 0;
1146
1147 // Clear destination buffer before sending the command 0x80 = average.
1148 memset(dest, 0x80, bufferlength);
1149
1150 // Set up FPGA, 125kHz
1151 // Wait for config.. (192+8190xPOW)x8 == 67ms
1152 LFSetupFPGAForADC(0, true);
1153
1154 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1155 SpinDelayUs(START_GAP);
1156
1157 // Opcode
1158 T55xxWriteBit(1);
1159 T55xxWriteBit(0); //Page 0
1160 if (PwdMode == 1){
1161 // Pwd
1162 for (i = 0x80000000; i != 0; i >>= 1)
1163 T55xxWriteBit(Pwd & i);
1164 }
1165 // Lock bit
1166 T55xxWriteBit(0);
1167 // Block
1168 for (i = 0x04; i != 0; i >>= 1)
1169 T55xxWriteBit(Block & i);
1170
1171 // Turn field on to read the response
1172 TurnReadLFOn();
1173
1174 // Now do the acquisition
1175 i = 0;
1176 for(;;) {
1177 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1178 AT91C_BASE_SSC->SSC_THR = 0x43;
1179 //AT91C_BASE_SSC->SSC_THR = 0xff;
1180 LED_D_ON();
1181 }
1182 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1183 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1184 ++i;
1185 LED_D_OFF();
1186 if (i > bufferlength) break;
1187 }
1188 }
1189
1190 cmd_send(CMD_ACK,0,0,0,0,0);
1191 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1192 LED_D_OFF();
1193 }
1194
1195 // Read card traceability data (page 1)
1196 void T55xxReadTrace(void){
1197 uint8_t *dest = get_bigbufptr_recvrespbuf();
1198 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1199 uint32_t i = 0;
1200
1201 // Clear destination buffer before sending the command 0x80 = average
1202 memset(dest, 0x80, bufferlength);
1203
1204 LFSetupFPGAForADC(0, true);
1205
1206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1207 SpinDelayUs(START_GAP);
1208
1209 // Opcode
1210 T55xxWriteBit(1);
1211 T55xxWriteBit(1); //Page 1
1212
1213 // Turn field on to read the response
1214 TurnReadLFOn();
1215
1216 // Now do the acquisition
1217 for(;;) {
1218 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1219 AT91C_BASE_SSC->SSC_THR = 0x43;
1220 LED_D_ON();
1221 }
1222 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1223 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1224 ++i;
1225 LED_D_OFF();
1226
1227 if (i >= bufferlength) break;
1228 }
1229 }
1230
1231 cmd_send(CMD_ACK,0,0,0,0,0);
1232 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1233 LED_D_OFF();
1234 }
1235
1236 void TurnReadLFOn(){
1237 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1238 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1239 // Give it a bit of time for the resonant antenna to settle.
1240 //SpinDelay(30);
1241 SpinDelayUs(8*150);
1242 }
1243
1244 /*-------------- Cloning routines -----------*/
1245 // Copy HID id to card and setup block 0 config
1246 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1247 {
1248 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1249 int last_block = 0;
1250
1251 if (longFMT){
1252 // Ensure no more than 84 bits supplied
1253 if (hi2>0xFFFFF) {
1254 DbpString("Tags can only have 84 bits.");
1255 return;
1256 }
1257 // Build the 6 data blocks for supplied 84bit ID
1258 last_block = 6;
1259 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1260 for (int i=0;i<4;i++) {
1261 if (hi2 & (1<<(19-i)))
1262 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1263 else
1264 data1 |= (1<<((3-i)*2)); // 0 -> 01
1265 }
1266
1267 data2 = 0;
1268 for (int i=0;i<16;i++) {
1269 if (hi2 & (1<<(15-i)))
1270 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1271 else
1272 data2 |= (1<<((15-i)*2)); // 0 -> 01
1273 }
1274
1275 data3 = 0;
1276 for (int i=0;i<16;i++) {
1277 if (hi & (1<<(31-i)))
1278 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1279 else
1280 data3 |= (1<<((15-i)*2)); // 0 -> 01
1281 }
1282
1283 data4 = 0;
1284 for (int i=0;i<16;i++) {
1285 if (hi & (1<<(15-i)))
1286 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1287 else
1288 data4 |= (1<<((15-i)*2)); // 0 -> 01
1289 }
1290
1291 data5 = 0;
1292 for (int i=0;i<16;i++) {
1293 if (lo & (1<<(31-i)))
1294 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1295 else
1296 data5 |= (1<<((15-i)*2)); // 0 -> 01
1297 }
1298
1299 data6 = 0;
1300 for (int i=0;i<16;i++) {
1301 if (lo & (1<<(15-i)))
1302 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1303 else
1304 data6 |= (1<<((15-i)*2)); // 0 -> 01
1305 }
1306 }
1307 else {
1308 // Ensure no more than 44 bits supplied
1309 if (hi>0xFFF) {
1310 DbpString("Tags can only have 44 bits.");
1311 return;
1312 }
1313
1314 // Build the 3 data blocks for supplied 44bit ID
1315 last_block = 3;
1316
1317 data1 = 0x1D000000; // load preamble
1318
1319 for (int i=0;i<12;i++) {
1320 if (hi & (1<<(11-i)))
1321 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1322 else
1323 data1 |= (1<<((11-i)*2)); // 0 -> 01
1324 }
1325
1326 data2 = 0;
1327 for (int i=0;i<16;i++) {
1328 if (lo & (1<<(31-i)))
1329 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1330 else
1331 data2 |= (1<<((15-i)*2)); // 0 -> 01
1332 }
1333
1334 data3 = 0;
1335 for (int i=0;i<16;i++) {
1336 if (lo & (1<<(15-i)))
1337 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1338 else
1339 data3 |= (1<<((15-i)*2)); // 0 -> 01
1340 }
1341 }
1342
1343 LED_D_ON();
1344 // Program the data blocks for supplied ID
1345 // and the block 0 for HID format
1346 T55xxWriteBlock(data1,1,0,0);
1347 T55xxWriteBlock(data2,2,0,0);
1348 T55xxWriteBlock(data3,3,0,0);
1349
1350 if (longFMT) { // if long format there are 6 blocks
1351 T55xxWriteBlock(data4,4,0,0);
1352 T55xxWriteBlock(data5,5,0,0);
1353 T55xxWriteBlock(data6,6,0,0);
1354 }
1355
1356 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1357 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1358 T55x7_MODULATION_FSK2a |
1359 last_block << T55x7_MAXBLOCK_SHIFT,
1360 0,0,0);
1361
1362 LED_D_OFF();
1363
1364 DbpString("DONE!");
1365 }
1366
1367 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1368 {
1369 int data1=0, data2=0; //up to six blocks for long format
1370
1371 data1 = hi; // load preamble
1372 data2 = lo;
1373
1374 LED_D_ON();
1375 // Program the data blocks for supplied ID
1376 // and the block 0 for HID format
1377 T55xxWriteBlock(data1,1,0,0);
1378 T55xxWriteBlock(data2,2,0,0);
1379
1380 //Config Block
1381 T55xxWriteBlock(0x00147040,0,0,0);
1382 LED_D_OFF();
1383
1384 DbpString("DONE!");
1385 }
1386
1387 // Define 9bit header for EM410x tags
1388 #define EM410X_HEADER 0x1FF
1389 #define EM410X_ID_LENGTH 40
1390
1391 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1392 {
1393 int i, id_bit;
1394 uint64_t id = EM410X_HEADER;
1395 uint64_t rev_id = 0; // reversed ID
1396 int c_parity[4]; // column parity
1397 int r_parity = 0; // row parity
1398 uint32_t clock = 0;
1399
1400 // Reverse ID bits given as parameter (for simpler operations)
1401 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1402 if (i < 32) {
1403 rev_id = (rev_id << 1) | (id_lo & 1);
1404 id_lo >>= 1;
1405 } else {
1406 rev_id = (rev_id << 1) | (id_hi & 1);
1407 id_hi >>= 1;
1408 }
1409 }
1410
1411 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1412 id_bit = rev_id & 1;
1413
1414 if (i % 4 == 0) {
1415 // Don't write row parity bit at start of parsing
1416 if (i)
1417 id = (id << 1) | r_parity;
1418 // Start counting parity for new row
1419 r_parity = id_bit;
1420 } else {
1421 // Count row parity
1422 r_parity ^= id_bit;
1423 }
1424
1425 // First elements in column?
1426 if (i < 4)
1427 // Fill out first elements
1428 c_parity[i] = id_bit;
1429 else
1430 // Count column parity
1431 c_parity[i % 4] ^= id_bit;
1432
1433 // Insert ID bit
1434 id = (id << 1) | id_bit;
1435 rev_id >>= 1;
1436 }
1437
1438 // Insert parity bit of last row
1439 id = (id << 1) | r_parity;
1440
1441 // Fill out column parity at the end of tag
1442 for (i = 0; i < 4; ++i)
1443 id = (id << 1) | c_parity[i];
1444
1445 // Add stop bit
1446 id <<= 1;
1447
1448 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1449 LED_D_ON();
1450
1451 // Write EM410x ID
1452 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1453 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1454
1455 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1456 if (card) {
1457 // Clock rate is stored in bits 8-15 of the card value
1458 clock = (card & 0xFF00) >> 8;
1459 Dbprintf("Clock rate: %d", clock);
1460 switch (clock)
1461 {
1462 case 32:
1463 clock = T55x7_BITRATE_RF_32;
1464 break;
1465 case 16:
1466 clock = T55x7_BITRATE_RF_16;
1467 break;
1468 case 0:
1469 // A value of 0 is assumed to be 64 for backwards-compatibility
1470 // Fall through...
1471 case 64:
1472 clock = T55x7_BITRATE_RF_64;
1473 break;
1474 default:
1475 Dbprintf("Invalid clock rate: %d", clock);
1476 return;
1477 }
1478
1479 // Writing configuration for T55x7 tag
1480 T55xxWriteBlock(clock |
1481 T55x7_MODULATION_MANCHESTER |
1482 2 << T55x7_MAXBLOCK_SHIFT,
1483 0, 0, 0);
1484 }
1485 else
1486 // Writing configuration for T5555(Q5) tag
1487 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1488 T5555_MODULATION_MANCHESTER |
1489 2 << T5555_MAXBLOCK_SHIFT,
1490 0, 0, 0);
1491
1492 LED_D_OFF();
1493 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1494 (uint32_t)(id >> 32), (uint32_t)id);
1495 }
1496
1497 // Clone Indala 64-bit tag by UID to T55x7
1498 void CopyIndala64toT55x7(int hi, int lo)
1499 {
1500 //Program the 2 data blocks for supplied 64bit UID
1501 // and the block 0 for Indala64 format
1502 T55xxWriteBlock(hi,1,0,0);
1503 T55xxWriteBlock(lo,2,0,0);
1504 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1505 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1506 T55x7_MODULATION_PSK1 |
1507 2 << T55x7_MAXBLOCK_SHIFT,
1508 0, 0, 0);
1509 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1510 // T5567WriteBlock(0x603E1042,0);
1511
1512 DbpString("DONE!");
1513 }
1514
1515 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1516 {
1517 //Program the 7 data blocks for supplied 224bit UID
1518 // and the block 0 for Indala224 format
1519 T55xxWriteBlock(uid1,1,0,0);
1520 T55xxWriteBlock(uid2,2,0,0);
1521 T55xxWriteBlock(uid3,3,0,0);
1522 T55xxWriteBlock(uid4,4,0,0);
1523 T55xxWriteBlock(uid5,5,0,0);
1524 T55xxWriteBlock(uid6,6,0,0);
1525 T55xxWriteBlock(uid7,7,0,0);
1526 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1527 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1528 T55x7_MODULATION_PSK1 |
1529 7 << T55x7_MAXBLOCK_SHIFT,
1530 0,0,0);
1531 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1532 // T5567WriteBlock(0x603E10E2,0);
1533
1534 DbpString("DONE!");
1535 }
1536
1537
1538 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1539 #define max(x,y) ( x<y ? y:x)
1540
1541 int DemodPCF7931(uint8_t **outBlocks) {
1542 uint8_t BitStream[256];
1543 uint8_t Blocks[8][16];
1544 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1545 int GraphTraceLen = sizeof(BigBuf);
1546 int i, j, lastval, bitidx, half_switch;
1547 int clock = 64;
1548 int tolerance = clock / 8;
1549 int pmc, block_done;
1550 int lc, warnings = 0;
1551 int num_blocks = 0;
1552 int lmin=128, lmax=128;
1553 uint8_t dir;
1554
1555 AcquireRawAdcSamples125k(0);
1556
1557 lmin = 64;
1558 lmax = 192;
1559
1560 i = 2;
1561
1562 /* Find first local max/min */
1563 if(GraphBuffer[1] > GraphBuffer[0]) {
1564 while(i < GraphTraceLen) {
1565 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1566 break;
1567 i++;
1568 }
1569 dir = 0;
1570 }
1571 else {
1572 while(i < GraphTraceLen) {
1573 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1574 break;
1575 i++;
1576 }
1577 dir = 1;
1578 }
1579
1580 lastval = i++;
1581 half_switch = 0;
1582 pmc = 0;
1583 block_done = 0;
1584
1585 for (bitidx = 0; i < GraphTraceLen; i++)
1586 {
1587 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1588 {
1589 lc = i - lastval;
1590 lastval = i;
1591
1592 // Switch depending on lc length:
1593 // Tolerance is 1/8 of clock rate (arbitrary)
1594 if (abs(lc-clock/4) < tolerance) {
1595 // 16T0
1596 if((i - pmc) == lc) { /* 16T0 was previous one */
1597 /* It's a PMC ! */
1598 i += (128+127+16+32+33+16)-1;
1599 lastval = i;
1600 pmc = 0;
1601 block_done = 1;
1602 }
1603 else {
1604 pmc = i;
1605 }
1606 } else if (abs(lc-clock/2) < tolerance) {
1607 // 32TO
1608 if((i - pmc) == lc) { /* 16T0 was previous one */
1609 /* It's a PMC ! */
1610 i += (128+127+16+32+33)-1;
1611 lastval = i;
1612 pmc = 0;
1613 block_done = 1;
1614 }
1615 else if(half_switch == 1) {
1616 BitStream[bitidx++] = 0;
1617 half_switch = 0;
1618 }
1619 else
1620 half_switch++;
1621 } else if (abs(lc-clock) < tolerance) {
1622 // 64TO
1623 BitStream[bitidx++] = 1;
1624 } else {
1625 // Error
1626 warnings++;
1627 if (warnings > 10)
1628 {
1629 Dbprintf("Error: too many detection errors, aborting.");
1630 return 0;
1631 }
1632 }
1633
1634 if(block_done == 1) {
1635 if(bitidx == 128) {
1636 for(j=0; j<16; j++) {
1637 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1638 64*BitStream[j*8+6]+
1639 32*BitStream[j*8+5]+
1640 16*BitStream[j*8+4]+
1641 8*BitStream[j*8+3]+
1642 4*BitStream[j*8+2]+
1643 2*BitStream[j*8+1]+
1644 BitStream[j*8];
1645 }
1646 num_blocks++;
1647 }
1648 bitidx = 0;
1649 block_done = 0;
1650 half_switch = 0;
1651 }
1652 if(i < GraphTraceLen)
1653 {
1654 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1655 else dir = 1;
1656 }
1657 }
1658 if(bitidx==255)
1659 bitidx=0;
1660 warnings = 0;
1661 if(num_blocks == 4) break;
1662 }
1663 memcpy(outBlocks, Blocks, 16*num_blocks);
1664 return num_blocks;
1665 }
1666
1667 int IsBlock0PCF7931(uint8_t *Block) {
1668 // Assume RFU means 0 :)
1669 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1670 return 1;
1671 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1672 return 1;
1673 return 0;
1674 }
1675
1676 int IsBlock1PCF7931(uint8_t *Block) {
1677 // Assume RFU means 0 :)
1678 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1679 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1680 return 1;
1681
1682 return 0;
1683 }
1684 #define ALLOC 16
1685
1686 void ReadPCF7931() {
1687 uint8_t Blocks[8][17];
1688 uint8_t tmpBlocks[4][16];
1689 int i, j, ind, ind2, n;
1690 int num_blocks = 0;
1691 int max_blocks = 8;
1692 int ident = 0;
1693 int error = 0;
1694 int tries = 0;
1695
1696 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1697
1698 do {
1699 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1700 n = DemodPCF7931((uint8_t**)tmpBlocks);
1701 if(!n)
1702 error++;
1703 if(error==10 && num_blocks == 0) {
1704 Dbprintf("Error, no tag or bad tag");
1705 return;
1706 }
1707 else if (tries==20 || error==10) {
1708 Dbprintf("Error reading the tag");
1709 Dbprintf("Here is the partial content");
1710 goto end;
1711 }
1712
1713 for(i=0; i<n; i++)
1714 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1715 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1716 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1717 if(!ident) {
1718 for(i=0; i<n; i++) {
1719 if(IsBlock0PCF7931(tmpBlocks[i])) {
1720 // Found block 0 ?
1721 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1722 // Found block 1!
1723 // \o/
1724 ident = 1;
1725 memcpy(Blocks[0], tmpBlocks[i], 16);
1726 Blocks[0][ALLOC] = 1;
1727 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1728 Blocks[1][ALLOC] = 1;
1729 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1730 // Debug print
1731 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1732 num_blocks = 2;
1733 // Handle following blocks
1734 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1735 if(j==n) j=0;
1736 if(j==i) break;
1737 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1738 Blocks[ind2][ALLOC] = 1;
1739 }
1740 break;
1741 }
1742 }
1743 }
1744 }
1745 else {
1746 for(i=0; i<n; i++) { // Look for identical block in known blocks
1747 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1748 for(j=0; j<max_blocks; j++) {
1749 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1750 // Found an identical block
1751 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1752 if(ind2 < 0)
1753 ind2 = max_blocks;
1754 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1755 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1756 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1757 Blocks[ind2][ALLOC] = 1;
1758 num_blocks++;
1759 if(num_blocks == max_blocks) goto end;
1760 }
1761 }
1762 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1763 if(ind2 > max_blocks)
1764 ind2 = 0;
1765 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1766 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1767 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1768 Blocks[ind2][ALLOC] = 1;
1769 num_blocks++;
1770 if(num_blocks == max_blocks) goto end;
1771 }
1772 }
1773 }
1774 }
1775 }
1776 }
1777 }
1778 tries++;
1779 if (BUTTON_PRESS()) return;
1780 } while (num_blocks != max_blocks);
1781 end:
1782 Dbprintf("-----------------------------------------");
1783 Dbprintf("Memory content:");
1784 Dbprintf("-----------------------------------------");
1785 for(i=0; i<max_blocks; i++) {
1786 if(Blocks[i][ALLOC]==1)
1787 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1788 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1789 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1790 else
1791 Dbprintf("<missing block %d>", i);
1792 }
1793 Dbprintf("-----------------------------------------");
1794
1795 return ;
1796 }
1797
1798
1799 //-----------------------------------
1800 // EM4469 / EM4305 routines
1801 //-----------------------------------
1802 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1803 #define FWD_CMD_WRITE 0xA
1804 #define FWD_CMD_READ 0x9
1805 #define FWD_CMD_DISABLE 0x5
1806
1807
1808 uint8_t forwardLink_data[64]; //array of forwarded bits
1809 uint8_t * forward_ptr; //ptr for forward message preparation
1810 uint8_t fwd_bit_sz; //forwardlink bit counter
1811 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1812
1813 //====================================================================
1814 // prepares command bits
1815 // see EM4469 spec
1816 //====================================================================
1817 //--------------------------------------------------------------------
1818 uint8_t Prepare_Cmd( uint8_t cmd ) {
1819 //--------------------------------------------------------------------
1820
1821 *forward_ptr++ = 0; //start bit
1822 *forward_ptr++ = 0; //second pause for 4050 code
1823
1824 *forward_ptr++ = cmd;
1825 cmd >>= 1;
1826 *forward_ptr++ = cmd;
1827 cmd >>= 1;
1828 *forward_ptr++ = cmd;
1829 cmd >>= 1;
1830 *forward_ptr++ = cmd;
1831
1832 return 6; //return number of emited bits
1833 }
1834
1835 //====================================================================
1836 // prepares address bits
1837 // see EM4469 spec
1838 //====================================================================
1839
1840 //--------------------------------------------------------------------
1841 uint8_t Prepare_Addr( uint8_t addr ) {
1842 //--------------------------------------------------------------------
1843
1844 register uint8_t line_parity;
1845
1846 uint8_t i;
1847 line_parity = 0;
1848 for(i=0;i<6;i++) {
1849 *forward_ptr++ = addr;
1850 line_parity ^= addr;
1851 addr >>= 1;
1852 }
1853
1854 *forward_ptr++ = (line_parity & 1);
1855
1856 return 7; //return number of emited bits
1857 }
1858
1859 //====================================================================
1860 // prepares data bits intreleaved with parity bits
1861 // see EM4469 spec
1862 //====================================================================
1863
1864 //--------------------------------------------------------------------
1865 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1866 //--------------------------------------------------------------------
1867
1868 register uint8_t line_parity;
1869 register uint8_t column_parity;
1870 register uint8_t i, j;
1871 register uint16_t data;
1872
1873 data = data_low;
1874 column_parity = 0;
1875
1876 for(i=0; i<4; i++) {
1877 line_parity = 0;
1878 for(j=0; j<8; j++) {
1879 line_parity ^= data;
1880 column_parity ^= (data & 1) << j;
1881 *forward_ptr++ = data;
1882 data >>= 1;
1883 }
1884 *forward_ptr++ = line_parity;
1885 if(i == 1)
1886 data = data_hi;
1887 }
1888
1889 for(j=0; j<8; j++) {
1890 *forward_ptr++ = column_parity;
1891 column_parity >>= 1;
1892 }
1893 *forward_ptr = 0;
1894
1895 return 45; //return number of emited bits
1896 }
1897
1898 //====================================================================
1899 // Forward Link send function
1900 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1901 // fwd_bit_count set with number of bits to be sent
1902 //====================================================================
1903 void SendForward(uint8_t fwd_bit_count) {
1904
1905 fwd_write_ptr = forwardLink_data;
1906 fwd_bit_sz = fwd_bit_count;
1907
1908 LED_D_ON();
1909
1910 //Field on
1911 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1912 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1913 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1914
1915 // Give it a bit of time for the resonant antenna to settle.
1916 // And for the tag to fully power up
1917 SpinDelay(150);
1918
1919 // force 1st mod pulse (start gap must be longer for 4305)
1920 fwd_bit_sz--; //prepare next bit modulation
1921 fwd_write_ptr++;
1922 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1923 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1924 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1925 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1926 SpinDelayUs(16*8); //16 cycles on (8us each)
1927
1928 // now start writting
1929 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1930 if(((*fwd_write_ptr++) & 1) == 1)
1931 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1932 else {
1933 //These timings work for 4469/4269/4305 (with the 55*8 above)
1934 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1935 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1936 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1937 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1938 SpinDelayUs(9*8); //16 cycles on (8us each)
1939 }
1940 }
1941 }
1942
1943
1944 void EM4xLogin(uint32_t Password) {
1945
1946 uint8_t fwd_bit_count;
1947
1948 forward_ptr = forwardLink_data;
1949 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1950 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1951
1952 SendForward(fwd_bit_count);
1953
1954 //Wait for command to complete
1955 SpinDelay(20);
1956
1957 }
1958
1959 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1960
1961 uint8_t *dest = get_bigbufptr_recvrespbuf();
1962 uint16_t bufferlength = 12000;
1963 uint32_t i = 0;
1964
1965 // Clear destination buffer before sending the command 0x80 = average.
1966 memset(dest, 0x80, bufferlength);
1967
1968 uint8_t fwd_bit_count;
1969
1970 //If password mode do login
1971 if (PwdMode == 1) EM4xLogin(Pwd);
1972
1973 forward_ptr = forwardLink_data;
1974 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1975 fwd_bit_count += Prepare_Addr( Address );
1976
1977 // Connect the A/D to the peak-detected low-frequency path.
1978 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1979 // Now set up the SSC to get the ADC samples that are now streaming at us.
1980 FpgaSetupSsc();
1981
1982 SendForward(fwd_bit_count);
1983
1984 // // Turn field on to read the response
1985 // TurnReadLFOn();
1986
1987 // Now do the acquisition
1988 i = 0;
1989 for(;;) {
1990 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1991 AT91C_BASE_SSC->SSC_THR = 0x43;
1992 }
1993 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1994 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1995 ++i;
1996 if (i >= bufferlength) break;
1997 }
1998 }
1999
2000 cmd_send(CMD_ACK,0,0,0,0,0);
2001 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2002 LED_D_OFF();
2003 }
2004
2005 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2006
2007 uint8_t fwd_bit_count;
2008
2009 //If password mode do login
2010 if (PwdMode == 1) EM4xLogin(Pwd);
2011
2012 forward_ptr = forwardLink_data;
2013 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2014 fwd_bit_count += Prepare_Addr( Address );
2015 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2016
2017 SendForward(fwd_bit_count);
2018
2019 //Wait for write to complete
2020 SpinDelay(20);
2021 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2022 LED_D_OFF();
2023 }
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